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16 BIT risc processor for computer hardware

16 BIT risc processor for computer hardware ...
  Algorithm      VHDL     

WarmOS 16-BIT real mode operating systems

WarmOS is a 16-BIT real mode operating system written with compilation, it includes some of the basic functions of the operating system should have, support implementation of the COM file format, providing some system API for programmers to write programs, and from the kernel to support Chinese disp...
  OS Develop        ASM     

VHDL realization 8051 (full version)

VHDL realization 8051 (full version)...
  Algorithm      VHDL     

Adder Subber xilinx FPGA sp605

Adder/subber project for xilinx FPGA sp605...
  Embeded      VHDL     

VHDL obtaining quadrature

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; Library UNISIM; use UNISIM.vcomponents.all; --------------------------------------------------------------------...
  signal Processing      VHDL     

1602+DS18B20+PWM control

1602+DS18B20+PWM control...
  单片机        C     

Using FPGA Verilog HDL simulation class I2C communication

Using FPGA Verilog HDL simulation class I2C communication...
  verilog      Verilog     

digital to analog convertor using VHDL ams

Its a project baded on implementing digital to analog convertor using VHDL-AMS using behavourial as well as structural abstractions....
  vhdl      VHDL     

LCD 1602 codes HD44780 compatible

LCD 1602 codes HD44780 compatible DBASE III compiler HITEC PICC 9.83 6 online mode R/W foot grounded...
  SCM        C     

LCD 1604 codes HD44780 compatible

LCD 1604 codes HD44780 compatible DBASE III compiler HITEC PICC 9.83 6 online mode R/W foot grounded...
  SCM        C     

VTK arBITrary two-dimensional image trimming

VTK arBITrary two-dimensional image trimming program, very nice, by visual studio MFC...
  Graph        Visual C++     

SIMULINK MODEL FOR FINDING BIT ERROR RATE FOR QAM OFDM

OFDM WITH QAM MODULATION...
  Matlab        Matlab     

Countdown clock

VHDL countdown clock, Countdown to A,B at the same time, the LCD display...
  sock      VHDL     

FSMD with reg,mux,fib

An FSMD impemented in VHDL, with a mux,reg,fib function, tested on xilinx ide and implemented into FPGA...
  Embeded      VHDL     

Counter Impl sp605

A counter implementation for sp605 xilinx board...
  Embeded      VHDL     

i got this 16

i got this 16-BIT huffman codec from abroad website. we usually use 8-BIT huffman codec. this source code is especially useful for medical image process....
  Compress-Decompress algrithms        Visual C++     

New FPGA

New FPGA-based data BIT sync clock extraction (CDR) method...
  VHDL-FPGA-Verilog        Others     

FPGA VHDL...

FPGA VHDL...
  VHDL-FPGA-Verilog      VHDL     

Written in Verilog IP core, 512K 16

Written in Verilog IP core, 512K 16-BIT SRAM...
  VHDL-FPGA-Verilog        Others     

design cpu 16 BITs by verilog HDL....

design cpu 16 BITs by verilog HDL....
  VHDL-FPGA-Verilog      VHDL