Sponsored links

Top Source Codes

FPGA60 binary digital tube display VHDL CODE

FPGA design 60 binary counter, through 2 seven-segment digital tube that is out. CODE is straightforward, emulation through, loaded on the FPGA Development Board and show success. Useful CODEs to get started....
  vhdl      VHDL     

VHDL CODE for different adders

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- hi...
  vhdl      VHDL     

VHDL CODE for latch_ff_comb for d_comb ckt in VHDL

library ieee; use ieee.std_logic_1164.all; entity d_comb is     port(    enable:in std_logic;          d:in std_logic;          q:out std_logic); end d_comb; architecture rtl of d_comb is begin p...
  vhdl      VHDL     

VHDL CODE for Adder / Subtractor

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY adder IS PORT(Cin        : IN STD_LOGIC; Carry        : IN STD_LOGIC;  X,Y        : IN STD_LOGIC_VE...
  Matlab      VHDL     

RSA VHDL CODE

Here, we present the first available open-source 512 bit RSA core. This is an early prototype version of a full FIPS Certified 512-4096 capable RSA Crypto-core which will be on sale soon. The version provided, has not the same performance than the final product since it was a proof of concept tha...
  verilog      Verilog     

Blif2VHDL format conversion tool

A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source CODE (C++) included)....
  vhdl        C     

Realization virtual electric piano based on VHDL

This program design using VHDL language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...
  vhdl      VHDL     

VHDL simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several parts through QuartusII 9 compiler testing is feasible. CODE original containing syste...
  vhdl      VHDL     

VHDL CODE for counter

Here is the CODE for counter in VHDL. --signal slow_clk : std_logic := '0';  --signal clk_divider : std_logic_vector(23 downto 0) := x"000000"; -- Clock divider can be changed to suit application.  -- Clock (clk) is normally 50 MHz, so each clock cycle  -- is 20 ns. A clock...
  vhdl      VHDL     

Wavelet transform and VHDL

Wavelet transform in JPEG2000 part of the VHDL source CODE. JPEG2000 The core algorithm is based on Discrete Wavelet transform. Due to discrete Wavelet transform of excellent characteristics makes it became JPEG2000 of core coding technology: while, it can is good to elimination image data in th...
  vhdl      VHDL     

Radix-8 Booth EnCODEd Modulo

VHDL CODE for Radix-8 Booth EnCODEd Module  Multipliers With Adaptive Delay for High Dynamic Range Residue Number System...
  vhdl      VHDL     

Discrete Cosine Transform(DCT/IDCT) in VHDL

the Project aim is to design DCT and IDCT in VHDL. DCT is used in image compression to compress the JPEG image. This file contains DCT and IDCT blocks and top module which integrates two blocks and testbench to test the two modules....
  vhdl      VHDL     

Waveform generator and sine waveforms generator based on VHDL language

Waveform generator and sine waveforms generator based on VHDL language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to VHDL is also helpful to-This i...
  vhdl      VHDL     

VHDL CODE for multiplexer

VHDL program for multiplexer we can write 4:1 mux also like this its very simple CODE for beginers to understand...
  vhdl      VHDL     

ADC VHDL CODE

Using VHDI Dispaly character. shows a simulation of a properly working implementation of LCD controller hardware. This simulation demonstrates the way the disparate state machines work together. As the initialization sequence finishes, the command states of the main state machine begin....
  vhdl      VHDL     

verilog and VHDL files

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port( clk: in std_logic; rst: in std_logic; q1: out std_logic); end tff1; architecture behavioral of tff1 is signal q: std_logic; begin process(clk,rst) begin...
  vhdl      VHDL     

I2CVHDLASDASDADASD

Content is too short. Attention please: CODEs without good description will be deleted and you won't get any points. Please describe it better to get more points....
  vhdl      VHDL     

VHDL CODE for fulladder of Behavioral Model

TOOLS   REQUIRED               Simulation tool: modelsim or Xilink PROCEDURE 1. To start the programs click the modelsim software. 2. The main page is opened,click the file option to crea...
  vhdl      VHDL     

ALU and register file VHDL CODE

The main goals of this project is to design a simple processor based on the ALU and the register file, and then execute the design using the MODELSIM simulator This project provides a short description of our processor, the top level of the design; a simple ALU that...
  vhdl      VHDL     

VHDL for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
  vhdl      VHDL     

Hot Search Keywords


    Sponsored links
jigsaw puzzle delphi?mop=AddEntry&op=modload&name=hit 61?mop |  蓝牙文件传输系统(源代码)android?cmd=sign |  j2me&#36855 &#23467 Powered by Advanced Guestbook |  ili9320 and spi and pic32?name=hit 1 href= s 0 h&op=modload |  pid 18f4550|4 Powered By: Article Friendly Ultimate chee?m |  MFC 进程通信& sa=U& ei=WxwzUcCRD9K2hAf3tIDIBw& |  MFC 资源管理器?mop=AddEntry&op=modload&name=Guestb hit |  onvif source code |  atm example |  insql powered by discuz! x convert&ct=clnk |  z buffer triangle rasterization |  jpeg to bmp in ansi c?name=Guestbook |  ID3 c# |  sgpio pld?mop=AddEntry&op=modload&name=Guestbook&file=index |  iee papers|4 |  download grafcet animation flash?cmd=sign |  CPUStress |  CCD to Camera Transformation |  sgpio verilog testbench?mop=AddEntry&op=modload&name=Guestbo |  opencv panoramic?mop=AddEntry&name=Guestbook hit &op=modload |  kernel reload?mop=AddEntry&op=modload&name=Guestbo hit 8 hre |  CProtectedViewWindows |  skeleton ?mop=AddEntry&op=modload&name=Guestboo hit hit 2 h |  kvm切换器 powered by “powered by php |  sgpio pld Ultimate Guestbook Version fend?name=Guestbook& |  convert binary to decimal |  FIFA 5?mop=AddEntry&name=hit 1 hre hit 502 href=&op=modload |  ????????? Ultimate Guestbook Version |  RBF 神经网络 matlab |  树 mfc |  automatic car plate recognition?name=Gu hit hit 1&op=modload |  ili9341 atmega?mop=AddEntry&name=hi hi hit hit 1&op=modload |  gauss jordan java?mop=AddEntry&op=modload&name=Gue hit 31 h |  鎵撳紑鏂囦欢澶瑰璇濇 |  inurl:asp? mop=AddEntry& name=Guestbook&file=index and |  image skeletonization using Zhang suen thinning?mop=AddEntry |  ant hoc net Powered by: Maian Guestbook martelo&ct=clnk?mop= |  l298 arduino?mop=AddEntry&name=hit h hit hit 1 h&op=modload |  ASCII 压缩型BCD |  shells |  ASCII12 |  s 0 ? Powered By: Article Friendly Ultimate RK=0 RS=EN1VU |  Qt webcam capture Windows |  laplacian mesh deformation?mop=AddEntry&name=gue &op=modload |  Hardware Verification with C pdf |  NS2 p2p |  graphic 128x24 ASM pic16f877 |  image pairs j2me |  CPP READ cpu sequence |  CPP 读取主板信息 infomation ? zb path=test |  DHT11 ccs c?mop=AddEntry&name=hit 3 href= s 0 ve&op=modload |  NS2 code for routing protocols |  NS2 for UWB |  double ended priority queue?mop=AddEntry&op=modload&name=Gu |  GPIB ?mop=AddEntry&name=G hit 28 href= s 0 hit 1&op=modload |  Abakus VCL |  guestbook asp inurl:asp? ct=c?mop=AddEntry&actio?mop=AddEntr |  tftp client for linux?mop=AddEntry&op=modload&name=Gues hit |  C人事管理系统 |  how to draw a contour in visual C?mop=AddEntry&op=modload&na |  online boo |  I2C SLAVE?mop=AddEntry&op=modload&name=G hit 4 hr hit 9 hit |  ds2406 |  GUI STM32 SSD1289 Ultimate Guestbook Version 85?ct=clnk |  Multithreading serial communication baseom 51 |  AMBE 2020 vocoder c?mop=AddEntry&op=modload&name=Guestbook h |  bcb gdi |  JustinIO Powered by PHPLD Add Article ?name=Gue hit 12 hre |  rrc滤波器设计 c |  congestion control using fuzzy logic TCP |  congestion forecasting |  congestion detection by fuzzy using matlab |  AD采样滤波 |  radiobutton E8 87 AA E7 BB 98 |  AD转换 sch |  AD转换实验 2位显示 |  congestion controlr protocolls in heterogenous wireless netw |  congestion control protocol NS2|4 |  internetopenurl sample code?cmd=sign |  ThreadTimer Designed by: PHPLD Your Site Submit Article?m |  Remote Control aND 8 = 8 |  geospatial |  CPLD总线通信 |  fuzzy edge detection?mop=AddEntry&name=Guestbook &op=modload |  CPLEX solver for GENCO maintenance scheduling program |  matlab code for random ramber genaretor |  matlab code for randomised hough transform |  tetris spartan 3 VHDL code|4 |  matlab code for random number generator RK=0 RS=Rj3EiMnEheQt |  iar ds1820 crc powered by TPK Guestbook hardy?name=hi hi h |  icce Designed by: PHPLD Your Site Submit Article moor%?m |  matlab code for rayleigh distribution |  hide data audio file matlab code class=l onmousedown= retur |  8051 sound |  curl hfss powered by TPK Guestbook disc&ct=clnk?mop=AddEnt |  opencvuart |  inurl:asp? name=Guestboo hit&amp op=modload&amp mop=AddEntr |  opencvdemo |  QT RS232 Member Login to Submit Article serial& ct=clnk&pr |  opencvmfc |