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ALU of MIPS architecture

·   Successfully designed and implemented basic blocks of MIPS including 5 stages pipeline, stalling technique and data forwarding. ·   Designed and implemented a Smart Scheduler that will help in reducing CPI, affected by stalling the pipeline for 1 clock cycle caus...
  verilog      Verilog     

Broadcom MIPS64 SOCs sample software

This is a collection of sample software related to the Broadcom(SiByte) BCM1125/H and BCM1250 MIPS64 SOCs.  For information about changes in this distribution, see the "version" file in this directory. Below is a list of the sample software directories which are provided, with...
  Communication        C     

Based on the MIPS architecture CPU

Written in Verilog CPU based on the MIPS architecture, you can run more than 50 pieces of instruction, including operations, branches, jumps, and other directives, but did not interrupt system, you might consider using, I am also a school curriculum course done ......
  verilog      Verilog     

MIPS instruction set matrix multiplication based implementation

Based on the MIPS64 instruction set, the Assembly realization the matrix multiplication, the simulator can enter the number of rows of the matrix, the number of columns of the matrix and other information, Then design your own calculation data matrix, or a more flexible, but it can also impro...
  Assembly Language        Others     

MIPS cross-compilation tools libraries

MIPS cross-compilation tools library, which contains a MIPS processor to compile and run programs on a variety of library files....
  处理器        C++     

LTE-FDD Femtocell Downlink simulator

The link path loss includes distance dependent path loss, shadow fading, fast fading and antenna gain. The simulation considers fast channel variation in both frequency and time domain. In each RB, the channel (link between TX and RX antenna) is assumed to be a complex white Gaussian random variable...
  Communication        Matlab     

Sun Moon simulator for the STM32-MINI-V3.0 dev board

Sun Moon simulator for the STM32-MINI-V3.0 dev board. Built for STM32F103RBT6 with ADS7843 touch screen and LCD 2.8" TFT controller ILI9325 Output     PB0 - LED Sun     PB1 - LED Moon     PA2 - LED1 on-board used for RTC seconds tick tock &nbs...
  Simulator - microcontroller        C     

SSDsim flash memory SSD simulator

SSDsim is an event-driven, modularly structured, and multi-tiered flash memory SSD simulator, which is capable of simulating most SSD hardware platforms, mainstream FTL schemes, allocation schemes, buffer management algorithms, and request scheduling algorithms. SSDsim is written in C, and it h...
  simulator        C     

NOAH routing in ns2 simulator

NOAH est un agent de routage sans fil (contrairement à DSDV, DSR, ...) ne prend en charge que les communications directes entre les noeuds sans fil ou entre stations de base et les noeuds mobiles. Cela permet de simuler des scénarios où le routage multi-saut est indésirable....
  network simulator        PDF     

I2C simulator Communication

i2c communication simulator. simulates a memory chip to i2c eeprom estiudar the coportamento chip implementation is possible and write the eeprom...
  Windows        C#     

A plc simulator

Here is my first version of PC PLC simulator program. I dreamed about it for almost 15 years and now my dream come true.  I’ll keep it as real as possible, if I have plenty of time. Any contribute is thankful. Programmable Logic Controller was designed for most industrial application...
  Windows        C++     

MIPS 程序

MIPS 处理器程序,出自于《CMOS VLSI Design and Systems Perspective》书中。可以实现LB、SB、RTYPE、BEQ、J指令,仿真测试可以用。...
  verilog      Verilog     

pipelineCPU_5stage_verilog

pipeline CPU with 5 stage: IF,ID,EX MEM,WB. Every module has a test bench. It contains a whole ISE project. You can run it directly. ROM module has pre-stored instruction as an instance....
  verilog      Verilog     

VHDL pipelined FIR Filter

This code describes a pipelined FIR filter (with 4 stages of pipeline). It takes as input the taps coefficients and provides the filtered samples. The number of taps is eight bits, the data width is fourteen bits. It is designed to deal with two's complement fixed point numbers....
  vhdl      VHDL     

pipeline coordinates locating algorithm based on integrated navigation technology

Geographic coordinate positioning question for long distance pipeline, based on integrated navigation technology is proposed and applied magnetic scalar pipeline geography Geographical coordinates of segment information revised pipeline location. The algorithm is based on basic principles of inerti...
  GIS        Matlab     

128 bit AES pipelined Cipher

The Advanced Encryption Standard (AES) specifies a FIPS- approved cryptographic algorithm that can be used to protect electronic data.  The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. This module is optimize...
  Crypt_Decrypt algrithms      Verilog     

RFIDSIM simulator

This is the main file in RFIDSIM simulator. This is used to summate RFID environment....
  Matlab        C++     

Atm simulator System

The Automated Teller Machine ATM Banking System is a banking application developed to perform different banking services through the Automated Teller Machines. The all functions include the regular transactions like cash deposits, cash withdrawals, balance enquiry, balance statements, savings accoun...
  Java Development        Java     

VMsimulator code

#include "main.h" int main(int argc, char** argv) {     int i, j, pageSize;     char* plist;     char* ptrace;     char* algorithm;     //Arguement checking and assignment     if(argc > 5)  ...
  Linux programming        C++     

IEC 870-5-101 master&slave simulators

One solution contains two VC++ projects (MS Visual studio 2008): IECMaster - simulator of IEC 870-5-101 communication protocol in MASTER mode,  IECSlave - the same in SLAVE mode.  Modbus - Modbus communication protocol library sources (used low level COM port routines)...
  Communication        C++     

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