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Four lights switch of marquee (marquee program in verilog_hdl languages)

This is a learning verilog hdl good information, suitable for beginners, explained in detail, from the light into the deep, learning the language, it is a hardware description language for good stuff, good material!...
  verilog      Verilog     

Using FPGA verilog hdl simulation class I2C communication

Using FPGA verilog hdl simulation class I2C communication...
  verilog      Verilog     

FPU Floating point unit verilog Vhdl

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...
  verilog      Verilog     

verilog and vhdl files

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port( clk: in std_logic; rst: in std_logic; q1: out std_logic); end tff1; architecture behavioral of tff1 is signal q: std_logic; begin process(clk,rst) begin...
  vhdl      VHDL     

Introduction to verilog

This article introduces the basics of verilog hdl language, to enable the beginner to quickly grasp the hdl Design methods, preliminary reports and to master the basics of verilog hdl language, to be able to read simple design code and Enough to make some simple verilog hdl design modeling...
  verilog      Verilog     

Floating-point multiply verilog FPGA

Digital multiplier, as an integral part of modern computers, their design work and more and more people's attention. This paper, hardware description languages verilog hdl design a floating-point multiplier based on complement one multiplication and design functions and better flexibility. Th...
  verilog      Verilog     

verilog simulation filters

verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

Blif2vhdl format conversion tool

A BLIF to Vhdl converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

DDR2 controller, verilog source code

Using verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...
  verilog      Verilog     

4-bit counters verilog code

One of the basics of verilog source code, binary counters for a 4. Both counts can be achieved to realize the frequency of the clock signal, so that is one very practical introduction to verilog code. On the basis of this code, you can make a variety of changes, to achieve different functionality....
  verilog      VHDL     

SOPC technology using verilog create Hello program

SOPC technology FPGA verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

DDS_Dual_ports verilog implementation

DDS_Dual_ports verilog implementation, you need to download experiment, according to their own needs to be modified in order to achieve the purpose of its...
  verilog      Verilog     

I2C verilog

I2C verilog files. Define a simple interface of I2C. After testing to ensure the using....
  verilog      Verilog     

verilog serial port serial port receive module receiver module

verilog serial port serial port receive module receiver module, contains the BPS modules, level detection module and the control module...
  verilog      Verilog     

Waveform generator and sine waveforms generator based on Vhdl language

Waveform generator and sine waveforms generator based on Vhdl language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to Vhdl is also helpful to-This i...
  vhdl      VHDL     

Realization virtual electric piano based on Vhdl

This program design using Vhdl language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...
  vhdl      VHDL     

Wavelet transform and Vhdl

Wavelet transform in JPEG2000 part of the Vhdl source code. JPEG2000 The core algorithm is based on Discrete Wavelet transform. Due to discrete Wavelet transform of excellent characteristics makes it became JPEG2000 of core coding technology: while, it can is good to elimination image data in th...
  vhdl      VHDL     

Face detection system designed using verilog

Face detection is designed using verilog which is designed for the implementation on DE-2 FPGA board. This project is designed to detect the human face when the camera input detects a human....
  verilog      Verilog     

FFT programs, based on verilog

FFT programs based on Vhdl language, 256, rotation factor exists to write your own ROM inside, multipliers and data storage using IP core, if it needs to use, you need to add IP core, cannot be run...
  verilog      VHDL     

Vhdl4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you start answering as a violation vie, violation vie waRNS players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...
  vhdl      VHDL     

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