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Rs232 using VHDL

Disign RS232 controller using VHDL on Altera DE2. This is a serial module which is useful for embed systems....
  vhdl      VHDL     

Adder in VHDL

This program is an  adder for two floating numbers using VHDL language....
  vhdl      VHDL     

Blif2VHDL format conversion tool

A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

VHDL frequency meter

Using the frequency meter VHDL write and modules divided into clear, basic principles for the detection of pulse signals in the life cycle of a gate frequency, use the four-segment digital tube display...
  vhdl      VHDL     

Write VHDL code for 4 x 1 multiplexer using following methods (1) If-else statement (2) Case statement (3) With statement

Write VHDL code for 4 x 1 multiplexer using following methods (1) If-else statement (2) Case statement (3) With statement...
  vhdl      VHDL     

Fast Vedic Mathematic Multiplication using VHDL

This document contains the detail contents for the vedic multiplier in VHDL. It contents the detial explaination of the vedic multiplier process....
  vhdl      VHDL     

Discrete Cosine Transform(DCT/IDCT) in VHDL

the Project aim is to design DCT and IDCT in VHDL. DCT is used in image compression to compress the JPEG image. This file contains DCT and IDCT blocks and top module which integrates two blocks and testbench to test the two modules....
  vhdl      VHDL     

3-wrie serial epROM controller

The code uses an FSM to interface a 3-wire serial eepROM with the fpga. It is an interface defined by MicroChip. The code stores the offset error fROM the ADC in the serial EPROM....
  vhdl      VHDL     

Waveform generator and sine waveforms generator based on VHDL language

Waveform generator and sine waveforms generator based on VHDL language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to VHDL is also helpful to-This i...
  vhdl      VHDL     

VHDL 100 examples

Share online for some 100 examples suitable for FPGA learning for beginners. Inside there are some classic tricks....
  vhdl      VHDL     

Realization virtual electric piano based on VHDL

This program design using VHDL language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...
  vhdl      VHDL     

Wavelet transform and VHDL

Wavelet transform in JPEG2000 part of the VHDL source code. JPEG2000 The core algorithm is based on Discrete Wavelet transform. Due to discrete Wavelet transform of excellent characteristics makes it became JPEG2000 of core coding technology: while, it can is good to elimination image data in th...
  vhdl      VHDL     

verilog and VHDL files

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port( clk: in std_logic; rst: in std_logic; q1: out std_logic); end tff1; architecture behavioral of tff1 is signal q: std_logic; begin process(clk,rst) begin...
  vhdl      VHDL     

BOOTH'S ALGORITHM STRUCTURAL VHDL CODE

BOOTH'S ALGORITHM IS USED FOR THE MULTIPLICATION OF TWO BINARY NUMBER IN COMPUTER ARCHITECTURE. AS THE PROCESSORS ARE GOOD IN SHIFTING OPERATION AND CANNOT EASILY DO THE MULTIPLICATION THAT'S WHY IT IS BEING USED....
  vhdl      VHDL     

VHDL code for latch_ff_comb for d_comb ckt in VHDL

library ieee; use ieee.std_logic_1164.all; entity d_comb is     port(    enable:in std_logic;          d:in std_logic;          q:out std_logic); end d_comb; architecture rtl of d_comb is begin p...
  vhdl      VHDL     

VHDL simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several parts through QuartusII 9 compiler testing is feasible. Code original containing syste...
  vhdl      VHDL     

VHDL for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
  vhdl      VHDL     

FPGA60 binary digital tube display VHDL code

FPGA design 60 binary counter, through 2 seven-segment digital tube that is out. Code is straightforward, emulation through, loaded on the FPGA Development Board and show success. Useful codes to get started....
  vhdl      VHDL     

Learn VHDL displays a six-digit

During the eight-digit seven-segment digital display control display on 8-bit 学号 , To display the 的 学号 You can ride Sequence changes, device validation error-free and running well....
  vhdl      VHDL     

VHDL4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you start answering as a violation vie, violation vie warns players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...
  vhdl      VHDL     

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