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Using FPGA verilog HDL simulation class I2C communication

Using FPGA verilog HDL simulation class I2C communication...
  verilog      Verilog     

Circulation information granulation source Test data based on SVM

Application of SVM and information methods of particle size, gas concentration prediction. Program is a normalized method, a method is not normalized....
  Matlab        Matlab     

To Test functioning of toolbox in matlab

To find functioning of toolbox in matlab...
  Matlab        Matlab     

Smallest but fasTest GUID generator function

This details how the shorTest CreateGUID function that uses API achieves its impressive speed.  The included simple Benchmark module pits it against other GUID generating routines. This file came from Planet-Source-Code The author may have retained certain copyrights to this code...
  Windows        VB     

2012Q4 China Internet Bandwidth SpeedTest Report

2012 national speed measured during the fourth quarter report data from http://www.speedTest.cn/...
  Other        Word     

Printer Testing control component sourcecodes

This is a printer Testing control component with sourcecodes...
  print        Visual C++     

Struts2 vulnerability Testing program

A Python script can detect the Struts2 command execution vulnerabilities. you can tie in with the fetching of search engine server....
  vulnerability detection        Python     

Information granulation method of SVM to prediction of gas concentration

Provide a forecast of new ideas, this method to prediction of gas concentration can be dynamically cycle, there are two: one is not normalized, a method is normalized...
  Matlab        Matlab     

82 VHDL, verilog Test case, involving a variety of grammatical rules. which is...

82 VHDL, verilog Test case, involving a variety of grammatical rules. which is you learn the HDL language helper....
  VHDL-FPGA-Verilog      VHDL     

USB1.1 IP core for device control, written with hardware describing language of...

USB1.1 IP core for device control, written with hardware describing language of verilog....
  VHDL-FPGA-Verilog        Others     

This is rs (255,223) verilog source coding. Inside : encode, decode, Test

This is rs (255,223) verilog source coding. Inside : encode, decode, Test-Bench and other documents....
  assembly language        Others     

verilog HDL prepared with VGA display driver...

verilog HDL prepared with VGA display driver...
  VHDL-FPGA-Verilog      VHDL     

Digital integrated circuits as hardware engineers, in the time to do the design,...

Digital integrated circuits as hardware engineers, in the time to do the design, writing Test Bench is very important, even more important than some of your design in itself, because it can determine whether your design can be used feasible, and can optimize your design....
  ARM-PowerPC-ColdFire-MIPS      VHDL     

encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorit...

encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field Test-Bench.v T...
  Compiler program        Others     

This leon3 design is tailored to the Altera NiosII Startix2 Development board,...

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the Test Bench cannot be simulated with DDR enabled...
  VHDL-FPGA-Verilog        Others     

In this case the compiler for each file is the order: 17_parity.vhd 17_Test_benc...

In this case the compiler for each file is the order: 17_parity.vhd 17_Test_Bench.vhd...
  Other systems      VHDL     

Language

Language- verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae....
  Communication      VHDL     

the laTest ATA

the laTest ATA-6 bus protocol source code reference, achieving DMA, PIO Mode, can be linked to CDROM, IDE hard drive, CF card....
  VHDL-FPGA-Verilog        Others     

Design and verification verilog_ examples Hdl classic books, strongly recommend....

Design and verification verilog_ examples Hdl classic books, strongly recommend...
  VHDL-FPGA-Verilog      VHDL     

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank...

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core TestBench has been written on Systemverilog and has been Tested in Modelsim. HSSDRC IP core is licensed under MIT License...
  VHDL-FPGA-Verilog      VHDL