Search VHDL FPGA Verilog floating point 16 bit division, 300 result(s) found

FPU floating point unit Verilog VHDL

2015-11-18 18:47    By:stoverson      View:277      Download:5

FPU (floating point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...

verilog Verilog

Using FPGA Verilog HDL simulation class I2C communication

2015-11-18 11:26    By:shigaofei      View:252      Download:0

Using FPGA Verilog HDL simulation class I2C communication...

verilog Verilog

Verilog Code for 8 bit array multiplier

2015-11-24 04:03    By:sonu      View:352      Download:5

I have written Verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

verilog VHDL

VHDL for 16 bit Time Domain Convolution

2015-11-04 10:24    By:liyangddd      View:76      Download:3

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...

vhdl VHDL

floating Multiplication in Verilog FPGA

2015-11-14 23:39      View:223      Download:5

The design of digital multiplier has received increasing attention as it becomes an indispensable part of modern computer. The paper introduces the design of a floating multiplier based on the compensate shifting in the hardware description language. The design can fulfill full function an...

verilog Verilog

VHDL and Verilog implementation of floating point multipliacation,ieee754

2015-10-31 20:23    By:bala      View:277      Download:0

Here are the steps again: First, convert the two representations to scientific notation. Thus, we explicitly represent the hidden 1. In this case, X is 1.01 X 22 and Y is 1.11 X 20. Let x be the exponent of&n...

Windows VHDL

VHDL and Verilog implementation of floating point adder ieee754

2015-10-31 20:22    By:bala      View:78      Download:1

IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier – all 0s is smallest exponent all 1s is largest – bias of 127 for single precision and 1023 for double precision – summary: (–1)sign × (1+significand)...

Windows VHDL

VHDL and Verilog implementation of clock 20 and 50 and 10 and 30 Mhz generation

2015-06-01 11:10    By:bala      View:89      Download:1

FPGA implemantaion of clock generation. if  i am working on 50 mhz clock generation i want to design clk counter with some clk 10mhz geneartion then what can i do for that one to implemneting 20mhz from 50mhz without using any ip core directly using coding tecniques we can imp...

Windows Verilog

Converts 24-bit map format is 16-bit bitmap format of the source code, including the format and RGB565 RGB555 format.

2015-11-11 08:39    By:shaoyan_lingli      View:508      Download:0

Source code is written entirely by me and tested to ensure that available.  You can convert 24 to 16 bitmap format bitmap format.  Enter the picture for 24-bit bitmap format, the output file format can be 16-bit map format.  The output format can be RGB555, RGB565 format can also b...

Image Processing C++

A 16-bit CRC program

2015-07-20 09:38    By:Wang007      View:48      Download:0

Written in c language to calculate the 16-bit CRC program entry parameters: data-the need to check array length-the number of bytes in the array...

Algorithm C


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