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FPU floating point unit Verilog VHDL

FPU (floating point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...
  verilog      Verilog     

Using FPGA Verilog HDL simulation class I2C communication

Using FPGA Verilog HDL simulation class I2C communication...
  verilog      Verilog     

Verilog Code for 8 bit array multiplier

I have written Verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....
  verilog      VHDL     

VHDL for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
  vhdl      VHDL     

floating-point multiply Verilog FPGA

Digital multiplier, as an integral part of modern computers, their design work and more and more people's attention. This paper, hardware description languages Verilog HDL design a floating-point multiplier based on complement one multiplication and design functions and better flexibility. Th...
  verilog      Verilog     

VHDL and Verilog implementation of floating point multipliacation,ieee754

Here are the steps again: First, convert the two representations to scientific notation. Thus, we explicitly represent the hidden 1. In this case, X is 1.01 X 22 and Y is 1.11 X 20. Let x be the exponent of&n...
  Windows      VHDL     

VHDL and Verilog implementation of floating point adder ieee754

IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier – all 0s is smallest exponent all 1s is largest – bias of 127 for single precision and 1023 for double precision – summary: (–1)sign × (1+significand)...
  Windows      VHDL     

VHDL and Verilog implementation of clock 20 and 50 and 10 and 30 Mhz generation

FPGA implemantaion of clock generation. if  i am working on 50 mhz clock generation i want to design clk counter with some clk 10mhz geneartion then what can i do for that one to implemneting 20mhz from 50mhz without using any ip core directly using coding tecniques we can imp...
  Windows      Verilog     

A 16-bit CRC program

Written in c language to calculate the 16-bit CRC program entry parameters: data-the need to check array length-the number of bytes in the array...
  Algorithm        C     

VHDL and Verilog implementation of dds and fft

The core component of a DDS waveform generator is the accumulator. The accumulator is a running counter which stores the current phase value of the generated waveform. The rate at which the accumulator is updated and the accumulator increment value determine the frequency of the generated waveform....
  Windows      VHDL     

16 bit risc processor for computer hardware

16 bit risc processor for computer hardware ...
  Algorithm      VHDL     

WarmOS 16-bit real mode operating systems

WarmOS is a 16-bit real mode operating system written with compilation, it includes some of the basic functions of the operating system should have, support implementation of the COM file format, providing some system API for programmers to write programs, and from the kernel to support Chinese disp...
  OS Develop        ASM     

16qam bit error rate simulation

Digital communication, many modulation schemes, 16QAM is often used, it is the amplitude and phase shift keying. QAM modulation consists of 16QAM, 32QAM, 64QAM, this code emulation 16QAM constellation diagram, and bit error rate BER and show the connections between them, and useful for learning and...
  Matlab        Matlab     

Auto meter software (Freescale 16 bit microcontroller)

Freescale Hz256 MCU. The complete program code, mainly used in automobile instrument development, stepper motors, LCD display, AD, interruption, timed with a very good reference....
  Embeded        C     

VGA color display the Verilog code for Xilinx FPGA

Verilog implementation of FPGA VGA sesser stripes display code, test absolutely right, can successfully implement functionality....
  verilog      Verilog     

Verilog DCT program

Discrete cosine transform DCT Testbench overall framework DCT Are most calculation-intensive piece of JPEG compression, image of the entire component image into 8  8 blocks, and input into a two-dimensional discrete cosine transform and realization of discrete cosine transform. DCT based on look...
  fpga      VHDL     

VHDL frequency meter

Using the frequency meter VHDL write and modules divided into clear, basic principles for the detection of pulse signals in the life cycle of a gate frequency, use the four-segment digital tube display...
  vhdl      VHDL     

FPGA VGA interface

VGA interface based on FPGA examples here, we must first consider vga_interface.v to support image resolutions, that is, 16x 16. So RAM Storage space required is 16bits x 16Words. RAM, like FIFO, to access the RAM when they are needed Up to xx_En_Sig signals. Because the RAM contains 16bits Write_...
  verilog      Verilog     

floating point multiplication

The Image and digital signal processing applications require high floating point calculations throughput, and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. floating point operations are hard to implement directly on FPGAs because of the complexity...
  verilog      Verilog     

8 bit adder Verilog

hey here is a ise format code for xilinx software Verilog 8 bit fixed point coding use this for example for coding with test bench...
  verilog      Verilog     

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