Sponsored links

Top Source Codes

FPU floating point unit Verilog VHDL

FPU (floating point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...
  verilog      Verilog     

Using FPGA Verilog HDL simulation class I2C communication

Using FPGA Verilog HDL simulation class I2C communication...
  verilog      Verilog     

VHDL for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
  vhdl      VHDL     

floating-point multiply Verilog FPGA

Digital multiplier, as an integral part of modern computers, their design work and more and more people's attention. This paper, hardware description languages Verilog HDL design a floating-point multiplier based on complement one multiplication and design functions and better flexibility. Th...
  verilog      Verilog     

VHDL and Verilog implementation of floating point multipliacation,ieee754

Here are the steps again: First, convert the two representations to scientific notation. Thus, we explicitly represent the hidden 1. In this case, X is 1.01 X 22 and Y is 1.11 X 20. Let x be the exponent of&n...
  Windows      VHDL     

VHDL and Verilog implementation of floating point adder ieee754

IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier – all 0s is smallest exponent all 1s is largest – bias of 127 for single precision and 1023 for double precision – summary: (–1)sign × (1+significand)...
  Windows      VHDL     

VHDL and Verilog implementation of clock 20 and 50 and 10 and 30 Mhz generation

FPGA implemantaion of clock generation. if  i am working on 50 mhz clock generation i want to design clk counter with some clk 10mhz geneartion then what can i do for that one to implemneting 20mhz from 50mhz without using any ip core directly using coding tecniques we can imp...
  Windows      Verilog     

VHDL and Verilog implementation of dds and fft

The core component of a DDS waveform generator is the accumulator. The accumulator is a running counter which stores the current phase value of the generated waveform. The rate at which the accumulator is updated and the accumulator increment value determine the frequency of the generated waveform....
  Windows      VHDL     

16 bit risc processor for computer hardware

16 bit risc processor for computer hardware ...
  Algorithm      VHDL     

WarmOS 16-bit real mode operating systems

WarmOS is a 16-bit real mode operating system written with compilation, it includes some of the basic functions of the operating system should have, support implementation of the COM file format, providing some system API for programmers to write programs, and from the kernel to support Chinese disp...
  OS Develop        ASM     

16qam bit error rate simulation

Digital communication, many modulation schemes, 16QAM is often used, it is the amplitude and phase shift keying. QAM modulation consists of 16QAM, 32QAM, 64QAM, this code emulation 16QAM constellation diagram, and bit error rate BER and show the connections between them, and useful for learning and...
  Matlab        Matlab     

Auto meter software (Freescale 16 bit microcontroller)

Freescale Hz256 MCU. The complete program code, mainly used in automobile instrument development, stepper motors, LCD display, AD, interruption, timed with a very good reference....
  Embeded        C     

floating point multiplication

The Image and digital signal processing applications require high floating point calculations throughput, and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. floating point operations are hard to implement directly on FPGAs because of the complexity...
  verilog      Verilog     

SOPC technology using Verilog create Hello program

SOPC technology FPGA Verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

FPGA reference design AD9267

High speed ADC AD9267 10bit FPGA reference design Verilog language Contains a Xilinx ISE12.2 Engineering...
  verilog      Verilog     

Full adder in Verilog

A simple Verilog code for full_adder. It is tested in both simulator and xilinx spartan3E FPGA board. ...
  verilog      Verilog     

Cheng Yuan FPGA design wireless communication coding

Book with the Xilinx FPGA development platform based on integrated FPGA technology and wireless communication in both directions, through the example of a large number of FPGA development, a more detailed description of the theory and implementation of wireless communication modules are frequently u...
  verilog      Verilog     

"Original" display __ __Verilog_ _FPGA control _1602 debugging notes

FPGA control principle and LCD1602 debugging notes source code This information came from Baidu bases (http://wenku.Baidu.com/) You now see the document is used to hold rice Baidu base generated by the Download Manager This document's original address from Thank you for your support Hold rice...
  verilog      Verilog     

Verilog for booth multiplier

We are going to propose a new SRAM bitcell for the purpose of less power consumption, read stability,less area than the existing Schmitt trigger based SRAM and other existing designs through a new design which is combined of virtual grounding with Read error reduction logic.  ...
  verilog      Verilog     

Verilog simulation filters

Verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

Hot Search Keywords


    Sponsored links
浣嶅鐞? |  浼犳煋鐥呰矾鐢? |  mp3 id3v1 |  图像 相似度 计算 |  radial basis function RBF neural network |  浼犳煋鐥呰矾鐢?cmd=sign |  浼犳煋鐥呰矾鐢 |  L6219 ?????mop=AddEntry&op=modload&name=Guestbo hit hit 1 |  ABC?? Powered by Advanced Guestbook Powered?cmd=sign |  warehouse C# Designed by: PHPLD Your Site Add Article RS= |  进化算法包括遗传算法 |  Tiffany I |  smearing algorithm in matlab?cmd=sign |  snake 5110 Powered by Advanced Guestbook close range?nam |  Jarr?mop=AddEntry&name=Guestb hit 2 hr hit hit 31&op=modload |  SELF HOLDING |  criminisi Designer: PHPLD Templates Submit Article?cmd=si |  CAN J1939 pic18 |  criminisi Designer: PHPLD Templates Submit Article |  EMV siren detector |  cc1101 255 |  zwterminatethread?mop=AddEntry&op=modload&name=Guestb hit 5 |  ?? Designed by One Way Links Add Article RK=0 |  MMC matlab |  image file read in matlab |  个人记事簿管理系统 |  逆变 |  vlc Windows |  对话框滚动简单实现 |  wordprocess |  beam matlab |  dfu stm32f103 Designer: PHPLD Templates Submit Article o |  16f1829 |  IMMDeviceEnumerator Powered by Advanced Guestbook UM?ct=cl |  HOG detection pedestrian |  ?cmd=sign |  18153 MGB OpenSource Guestbook outsource RK=0 RS=kMj2DLn9i |  HFSS human body MGB OpenSource Guestbook Hood?cmd=sign?pre |  webservice gsoap |  calculate a mathematical expression ctf= rdr T |  LogTemp MGB OpenSource Guestbook pencilled RK=0 RS=BVmByiQ |  rockchip MGB OpenSource Guestbook souls RK=0 RS=a0IqRC |  rockchip MGB OpenSource Guestbook souls RK=0 RS=OQTMGs2iIu |  18153 MGB OpenSource Guestbook outsource RK=0 RS=GUQSRhZdo |  rockchip MGB OpenSource Guestbook souls RK=0 RS=a0IqRCYwd |  rockchip MGB OpenSource Guestbook souls RK=0 RS=Oe09gmfm7B |  rockchip MGB OpenSource Guestbook souls RK=0 RS=brSU5tp3Rk |  Determining the matrix c code |  Haar hand gesture detection recognition matlab |  ELECTRICITY BILL PAYMENT PROJECT |  : Samsung DSB H670N ctf= rdr T |  aduc powered by TPK Guestbook we?name=Guestbook hit 14 hr |  sunplus DVD rom uploader Powered by: Maian Guestbook Tor?c |  frequency source ? hmc830 powered by TPK Guestbook makeu?c |  Borland C Builder des算法 |  kd 树 |  active countor |  Text hold |  s 0 s 0 vedic ADDER in vhdl inurl: edu guestbook move?cm |  hatmelrhl bau1026g |  robustSoliton?mode=register&agreed=true&iscanyesno=yeswecan |  udp 打洞服务器 c 源码 |  OFDM transceiver design using MATLAB simulation codes intext |  codesys pid Designer: PHPLD Templates Submit Article degra R |  mario game c |  qurdric power control |  ofdm 同步 编程 |  list control image list |  WinHTMLEditorControl?mode=register&agreed=true&isc?mop=AddEn |  数据包定义及发送接收 C |  QT opengl 閫憸 |  内存占用率曲线 |  VC 定时截屏 |  C 连接 ORACLE |  ????????? Ultimate Guestbook Version RK=0 RS=QarNnpHYBH3O8 |  RAS encryption Powered by Advanced Guestbook |  gomoku minimax alpha beta |  设备运行时间 源码 Powered by Advanced Guestbook |  ucgui user manual |  32 bit multiplier vhdl?mop=AddEntry&op=modload&name=G hit hi |  STM32F103 DAC Powered by Easy Guestbook error?cmd=sign?mop |  EVC 多线程 |  sffs matlab |  智慧卡 |  ?? ?? ?? po |  Matlabalgorithme perturbe and observe |  msc7832 |  CC2530 ds18b20 Designer: PHPLD Templates Submit Article?n |  ? RBF |  ?gif |  DELPHI SOCKET 应用 MODBUS tcp ip |  CC2530 ds18b20 Designer: PHPLD Templates Submit Article |  CC2530 ds18b20 Designer: PHPLD Templates Submit Article?c |  16F628A compilier |  素数测试 |  c51 sht10 |  MDS 源码 |  solar voltage regulator |  获取电脑当前运行情况 |  2d gaussian fit |