Sponsored links

Top Source Codes

FPU floating point unit Verilog VHDL

FPU (floating point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...
  verilog      Verilog     

Using FPGA Verilog HDL simulation class I2C communication

Using FPGA Verilog HDL simulation class I2C communication...
  verilog      Verilog     

VHDL for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
  vhdl      VHDL     

floating-point multiply Verilog FPGA

Digital multiplier, as an integral part of modern computers, their design work and more and more people's attention. This paper, hardware description languages Verilog HDL design a floating-point multiplier based on complement one multiplication and design functions and better flexibility. Th...
  verilog      Verilog     

VHDL and Verilog implementation of floating point multipliacation,ieee754

Here are the steps again: First, convert the two representations to scientific notation. Thus, we explicitly represent the hidden 1. In this case, X is 1.01 X 22 and Y is 1.11 X 20. Let x be the exponent of&n...
  Windows      VHDL     

VHDL and Verilog implementation of floating point adder ieee754

IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier – all 0s is smallest exponent all 1s is largest – bias of 127 for single precision and 1023 for double precision – summary: (–1)sign × (1+significand)...
  Windows      VHDL     

VHDL and Verilog implementation of clock 20 and 50 and 10 and 30 Mhz generation

FPGA implemantaion of clock generation. if  i am working on 50 mhz clock generation i want to design clk counter with some clk 10mhz geneartion then what can i do for that one to implemneting 20mhz from 50mhz without using any ip core directly using coding tecniques we can imp...
  Windows      Verilog     

VHDL and Verilog implementation of dds and fft

The core component of a DDS waveform generator is the accumulator. The accumulator is a running counter which stores the current phase value of the generated waveform. The rate at which the accumulator is updated and the accumulator increment value determine the frequency of the generated waveform....
  Windows      VHDL     

16 bit risc processor for computer hardware

16 bit risc processor for computer hardware ...
  Algorithm      VHDL     

WarmOS 16-bit real mode operating systems

WarmOS is a 16-bit real mode operating system written with compilation, it includes some of the basic functions of the operating system should have, support implementation of the COM file format, providing some system API for programmers to write programs, and from the kernel to support Chinese disp...
  OS Develop        ASM     

16qam bit error rate simulation

Digital communication, many modulation schemes, 16QAM is often used, it is the amplitude and phase shift keying. QAM modulation consists of 16QAM, 32QAM, 64QAM, this code emulation 16QAM constellation diagram, and bit error rate BER and show the connections between them, and useful for learning and...
  Matlab        Matlab     

Auto meter software (Freescale 16 bit microcontroller)

Freescale Hz256 MCU. The complete program code, mainly used in automobile instrument development, stepper motors, LCD display, AD, interruption, timed with a very good reference....
  Embeded        C     

floating point multiplication

The Image and digital signal processing applications require high floating point calculations throughput, and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. floating point operations are hard to implement directly on FPGAs because of the complexity...
  verilog      Verilog     

SOPC technology using Verilog create Hello program

SOPC technology FPGA Verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

FPGA reference design AD9267

High speed ADC AD9267 10bit FPGA reference design Verilog language Contains a Xilinx ISE12.2 Engineering...
  verilog      Verilog     

Cheng Yuan FPGA design wireless communication coding

Book with the Xilinx FPGA development platform based on integrated FPGA technology and wireless communication in both directions, through the example of a large number of FPGA development, a more detailed description of the theory and implementation of wireless communication modules are frequently u...
  verilog      Verilog     

"Original" display __ __Verilog_ _FPGA control _1602 debugging notes

FPGA control principle and LCD1602 debugging notes source code This information came from Baidu bases (http://wenku.Baidu.com/) You now see the document is used to hold rice Baidu base generated by the Download Manager This document's original address from Thank you for your support Hold rice...
  verilog      Verilog     

Verilog simulation filters

Verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

floating point adder

Verilog code coded in xilinx used to add 2 floating point numbers.... and the technique used in this coding is piplining........
  verilog      Verilog     

Verilog and VHDL files

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port( clk: in std_logic; rst: in std_logic; q1: out std_logic); end tff1; architecture behavioral of tff1 is signal q: std_logic; begin process(clk,rst) begin...
  vhdl      VHDL     

Hot Search Keywords


    Sponsored links
flash ?name=Guestbook?name=hit 10 href= s 0 Business i hi hi |  ? powered by advanced guestbook?et rp=1 inurl:1?mop=AddEntr |  7920????? |  ? quadratic Powered by Advanced Guestbook highway&ct=cln?c |  ? Powered by Advanced Guestbook=?action=add RS=^ADAiD4xTcv |  CMU 库 MGB OpenSource Guestbook hatchback?action=sign |  ? PPP Powered by Advanced Guestbook inter |  ? quadratic Powered by Advanced Guestbook highway&ct=cln |  ? Powered by Advanced Guestbook Powered Result: captch?h |  CyAPI of CY7c68001 |  simulation d un recepteur RF avec matlab |  lpc2478 rtos |  simulation of 3G cellular network |  cuda ocr Designed by One Way Links Add Article RK=0 RS=j |  sm501 qnx powered by TPK Guestbook jade?name=Guestbook |  QQ2010 高仿窗口 |  HarwDisk powered by Fireboard cabbage patch RK=0 RS=SAQw |  ? Powered by Advanced Guestbook=?action=add RS=^ADA7facdy0 |  ENC28J60 18F4550?name=Guestbook hit 2 hit 1 hr h hit 12 hre |  ?AI Powered by Advanced Guestbook?mop=AddEntry?op=modload?n |  ? ip ? ? powered by advanced guestbook lengthen?ct=?cmd=s |  ? Powered by Advanced Guestbook=%?cmd=sign?cmd=sign?cmd=sig |  ? inurl: edu guestbook mo% ** aND ** 8 = 8 |  ? Powered by Advanced Guestbook=?action=add?name=Guestbook |  DM385 Powered by Advanced Guestbook heating&ct=clnk?cmd=si |  RCS Radar powered by TPK Guestbook Balloon powered by TPK |  tcl script for wormhole attack in ns2?mop=AddEntry&op=modloa |  mscomm 440 |  ? Powered by Advanced Guestbook&q= Powered by Ad |  ? 2D 3D Powered by Advanced Guestbook amb |  GLONASS |  ?? Linux inurl: edu guestbook infrared?amp hl=zh |  ? ? Ultimate Guestbook Version?agbook=addentry?cmd=sign?cm |  10?16? Using Article Directory plugin RK=0 RS=X zTzEcaI4cVqs |  ??exe?? Powered by Advanced Guestbook appetizer& |  ?? 2D 3D Powered by Advanced Guestbook amb?mop=AddEntry&op |  ??chrome url Powered by Advanced Guestbook chrome?ct=c |  ?? hj1602a powered by advanced guestbook r?op=modload |  ???PPI?? Powered by Advanced Guestbook?cmd=sign?cmd=sign?mo |  ???PPI?? Powered by Advanced Guestbook?cmd=sign?cmd=sign |  ?? hj1602a powered by advanced guestbook r?op=modload& |  protel 数码管 |  ??exe ???? |  ???PPI?? Powered by Advanced Guestbook Powered R |  ? PHP Link Directory Submit Article ? RK=0 RS=C Ey |  ?? PHP Link Directory Submit Article ??&? RK=0 RS=Oz848OtT |  sm501 qnx powered by TPK Guestbook jade?mop=AddEntry&op=mo |  LRU 2 Designed by: PHPLD Your Site Add Article spare%3?c |  comparison between bpsk qpsk qam |  qt serial communication mini2440 |  android alarm clock |  用VC网的最大流最小割 |  i8255 |  windml font powered by advanced guestbook meteor |  navier stokes cavity |  FHMIPV6 ns2 |  hash openmp |  library management system using jdbc |  circle asm |  p code decompile matlab |  Solid motor |  matlab image filter soruce code |  win32 button |  DE& |  mt85xx |  ip Camera cgi Ultimate Guestbook Version rock?cmd=sign?mo |  rx12864 powered by TPK Guestbook the?cmd=sign |  sm501 qnx powered by TPK Guestbook jade |  opengl radar ppi display |  ??? Using Article Directory plugin |  massive mimo Advanced Guestbook footprints medical&ct=clnk |  KLT opencv |  english progmem Designed by: PHPLD Your Site Add Article%?m |  interfacing 8051 with IR |  SPO2 Monitoring powered by TPK Guestbook Balloon&ct=clnk?o |  msp430g2553 temperature |  简单的mysql jsp新闻发布 |  max entropy |  PCSC mifare2 Powered by Advanced Guestbook dynasty?name=Gu |  数字秒表, |  dsp 2833 |  computer graphics mini projects OPENGL RK=0 RS=jTmLkmxAvS48Q |  PCSC mifare2 Powered by Advanced Guestbook dynasty |  时间显示JS |  plot electric field matlab?ifile |  s 5 CStatic ?? guestbook?start= ??&tbs=qdr:?mop=AddEntry&op |  MPOE Ultimate Guestbook Version?action=sign? s?mop=AddE |  群聊插件 for openfire |  crossover in genetic algorithm |  宿舍管理系统源代码 |  tq 2440 jflash |  msp430 servomotor Powered by Easy Guestbook if RK=0 RS=oUq |  圆球体积 |  online ticket booking for movie show |  VNCViewer |  HarwDisk powered by Fireboard cabbage patch?tbs=qdr:w% RK=0 |  linphone鐢╭t缂栧啓鐣岄潰 |  带通采样 matlab |  28335 i2c powered by TPK Guestbook pedal&ct=clnk |  net video activex v23 cab hikvision |