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Using FPGA Verilog HDL simulation class I2C communication

Using FPGA Verilog HDL simulation class I2C communication...
  verilog      Verilog     

VHDL and Verilog implementation of clock 20 and 50 and 10 and 30 Mhz generation

FPGA implemantaion of clock generation. if  i am working on 50 mhz clock generation i want to design clk counter with some clk 10mhz geneartion then what can i do for that one to implemneting 20mhz from 50mhz without using any ip core directly using coding tecniques we can imp...
  Windows      Verilog     

VHDL and Verilog implementation of dds and fft

The core component of a DDS waveform generator is the accumulator. The accumulator is a running counter which stores the current phase value of the generated waveform. The rate at which the accumulator is updated and the accumulator increment value determine the frequency of the generated waveform....
  Windows      VHDL     

VHDL and Verilog implementation of floating point adder ieee754

IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier – all 0s is smallest exponent all 1s is largest – bias of 127 for single precision and 1023 for double precision – summary: (–1)sign × (1+significand)...
  Windows      VHDL     

VHDL and Verilog implementation of floating point multipliacation,ieee754

Here are the steps again: First, convert the two representations to scientific notation. Thus, we explicitly represent the hidden 1. In this case, X is 1.01 X 22 and Y is 1.11 X 20. Let x be the exponent of&n...
  Windows      VHDL     

Cheng Yuan FPGA design wireless communication coding

Book with the Xilinx FPGA development platform based on integrated FPGA technology and wireless communication in both directions, through the example of a large number of FPGA development, a more detailed description of the theory and implementation of wireless communication modules are frequently u...
  verilog      Verilog     

SOPC technology using Verilog create Hello program

SOPC technology FPGA Verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

FPGA source audio signal Analyzer

Audio signal through consists of the OPAMP and the resistance of the 50Ohm impedance matching circuit to meet the input impedance 50 Ohm system requirements, calculation of signal power. In order to ensure that this signal is undistorted sampled signals through the cut-off frequency for the 10Khz an...
  vhdl      VHDL     

"Original" display __ __Verilog_ _FPGA control _1602 debugging notes

FPGA control principle and LCD1602 debugging notes source code This information came from Baidu bases (http://wenku.Baidu.com/) You now see the document is used to hold rice Baidu base generated by the Download Manager This document's original address from Thank you for your support Hold rice...
  verilog      Verilog     

FPGA reference design AD9267

High speed ADC AD9267 10bit FPGA reference design Verilog language Contains a Xilinx ISE12.2 Engineering...
  verilog      Verilog     

Blif2VHDL format conversion tool

A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

Four lights switch of marquee (marquee program in Verilog_hdl languages)

This is a learning Verilog HDL good information, suitable for beginners, explained in detail, from the light into the deep, learning the language, it is a hardware description language for good stuff, good material!...
  verilog      Verilog     

Verilog simulation filters

Verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

FPGA'for' cycle

Written in the Verilog language for circulation and used to verify whether in the FPGA can writing a for loop in c, it turned out although the emulation to get the right result, but in real engineering are not compile-time takes 24 hours to complete, so I chose another method to loop through, after...
  verilog      Verilog     

FPGA60 binary digital tube display VHDL code

FPGA design 60 binary counter, through 2 seven-segment digital tube that is out. Code is straightforward, emulation through, loaded on the FPGA Development Board and show success. Useful codes to get started....
  vhdl      VHDL     

Floating-point multiply Verilog FPGA

Digital multiplier, as an integral part of modern computers, their design work and more and more people's attention. This paper, hardware description languages Verilog HDL design a floating-point multiplier based on complement one multiplication and design functions and better flexibility. Th...
  verilog      Verilog     

AD9469 FPGA code software-defined radio front-end

AD9469 FPGA code software-defined radio front-end AD9469 Verilog code After the FIFO data processing...
  verilog      Verilog     

Based on FPGA LCD1602 drivers

I ready to adopt LCD1602 Character LCD as a vehicle to achieve " Hello World" Displays. Similar to that in the preceding MCU key programme of eliminating jitter 1 c language code, like, here we are ready to state machines, transplant LCD1602 driver code to Verilog HDL And driving LCD1602, show tha...
  Verilog HDL      VHDL     

Hammond organ/music player based on FPGA device

1, can be used directly; 2, Verilog programming; 3, 16X16 matrix keyboard keystrokes can be realized; 4, you can play music of the butterfly lovers; 5, piano; 6, you can play the history of key value; 7, digital control can display key values in real time, is also...
  verilog      Verilog     

FPGA stopwatch

&Nbsp;Xilinx Spartan 6, on the seven-segment decoder tube display, press to control timing of start, end, and seconds add up-by-function Verilog code, at the same time it is a demo of this Board works, is also one of Sun Yat-sen University mobile information engineering coursework project. I hop...
  verilog      Verilog     

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