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Using FPGA Verilog HDL simulation class I2C communication

Using FPGA Verilog HDL simulation class I2C communication...
  verilog      Verilog     

VHDL and Verilog implementation of clock 20 and 50 and 10 and 30 Mhz generation

FPGA implemantaion of clock generation. if  i am working on 50 mhz clock generation i want to design clk counter with some clk 10mhz geneartion then what can i do for that one to implemneting 20mhz from 50mhz without using any ip core directly using coding tecniques we can imp...
  Windows      Verilog     

VHDL and Verilog implementation of dds and fft

The core component of a DDS waveform generator is the accumulator. The accumulator is a running counter which stores the current phase value of the generated waveform. The rate at which the accumulator is updated and the accumulator increment value determine the frequency of the generated waveform....
  Windows      VHDL     

VHDL and Verilog implementation of floating point adder ieee754

IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier – all 0s is smallest exponent all 1s is largest – bias of 127 for single precision and 1023 for double precision – summary: (–1)sign × (1+significand)...
  Windows      VHDL     

VHDL and Verilog implementation of floating point multipliacation,ieee754

Here are the steps again: First, convert the two representations to scientific notation. Thus, we explicitly represent the hidden 1. In this case, X is 1.01 X 22 and Y is 1.11 X 20. Let x be the exponent of&n...
  Windows      VHDL     

VHDL frequency meter

Using the frequency meter VHDL write and modules divided into clear, basic principles for the detection of pulse signals in the life cycle of a gate frequency, use the four-segment digital tube display...
  vhdl      VHDL     

EasyFPGA030 example code

This source code is the EasyFPGA030 example code. Welcome to download and try. Thank you all for your support!...
  verilog      Verilog     

Cheng Yuan FPGA design wireless communication coding

Book with the Xilinx FPGA development platform based on integrated FPGA technology and wireless communication in both directions, through the example of a large number of FPGA development, a more detailed description of the theory and implementation of wireless communication modules are frequently u...
  verilog      Verilog     

Digital Alarm Clock FPGA

The aim this project is to implement the functionality of a digital alarm clock on a FPGA. As soon as the FPGA is switched on, the clock starts. The alarm can be set using the dip-switches provided on the FPGA board. This is indicated through the LEDs of the corresponding dip swi...
  verilog      Verilog     

Design of UART based on FPGA

This is the more successful graduate students during the design of curriculum design. Prepared by Verilog to send, receive, has top-level modules! FPGA Development Board can be run....
  verilog      Verilog     

SOPC technology using Verilog create Hello program

SOPC technology FPGA Verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

Full adder in Verilog

A simple Verilog code for full_adder. It is tested in both simulator and xilinx spartan3E FPGA board. ...
  verilog      Verilog     

8 bit adder Verilog

hey here is a ise format code for xilinx software Verilog 8 bit fixed point coding use this for example for coding with test bench...
  verilog      Verilog     

Study on Turbo Code decoder and FPGA implementation.

Altera Quartus II software platform completed the decoding of Turbo codes based on Log-MAP algorithm for FPGA design and implementation. In Turbo yards of FPGA design and achieved part, main for has Turbo yards of compiled yards device in the all important module for has design and achieved, such as...
  vhdl      VHDL     

Adder in VHDL

This program is an  adder for two floating numbers using VHDL language....
  vhdl      VHDL     

Booth multiplier in Verilog

This file describes the code for booth multiplier in Verilog. the source code is simulated and verified for better results...
  verilog      Verilog     

Ledbanner in Verilog code using FPGA SPARTAN-3E

Ledbanner in Verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.  It will go from left to rigth or vise versa. And will reset fuction when press reset botton....
  verilog      Verilog     

FPGA source audio signal Analyzer

Audio signal through consists of the OPAMP and the resistance of the 50Ohm impedance matching circuit to meet the input impedance 50 Ohm system requirements, calculation of signal power. In order to ensure that this signal is undistorted sampled signals through the cut-off frequency for the 10Khz an...
  vhdl      VHDL     

"Original" display __ __Verilog_ _FPGA control _1602 debugging notes

FPGA control principle and LCD1602 debugging notes source code This information came from Baidu bases (http://wenku.Baidu.com/) You now see the document is used to hold rice Baidu base generated by the Download Manager This document's original address from Thank you for your support Hold rice...
  verilog      Verilog     

FPGA reference design AD9267

High speed ADC AD9267 10bit FPGA reference design Verilog language Contains a Xilinx ISE12.2 Engineering...
  verilog      Verilog     

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