library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
Library UNISIM;
use UNISIM.vcomponents.all;
--------------------------------------------------------------------... signal ProcessingVHDL
DE2-based video telephony part of the source code to achieve the video image capture, VGA display, LAN communications function... VHDL-FPGA-VerilogVHDL
This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency po... VHDL-FPGA-VerilogVHDL
Multi-function waveform generator and simulation of VHDL procedures URAT VHDL simulation procedures and ASK modulation and demodulation procedures and VHDL simulation program LCD control and simulation of VHDL... VHDL-FPGA-VerilogVHDL