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Full adder in verilog

A simple verilog code for full_adder. It is tested in both simulator and xilinx spartan3E fpga board. ...
  verilog      Verilog     

8 bit adder verilog

hey here is a ise format code for xilinx software verilog 8 bit fixed point coding use this for example for coding with test bench...
  verilog      Verilog     

VGA color display the verilog code for Xilinx FPGA

verilog implementation of FPGA VGA sesser stripes display code, test absolutely right, can successfully implement functionality....
  verilog      Verilog     

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...
  verilog      Verilog     

verilog examples

Learn verilog Common programming methods and examples. Welcome to download and trial. Thank you all for your support!...
  verilog      VHDL     

verilog jpeg

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bitstream necessary to build a jpeg image. The core was written in generic, regular verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores,...
  verilog      Verilog     

Parallel CRC verilog code generator

A parllel CRC verilog generator has been written in C++ to generate a parallel CRC verilog code for a given user defined data width and CRC polynomial. This is from outputlogic.com . This a direct implementation algorithm used in the website....
  verilog      Verilog     

Traffic light verilog HDL source code

It is the source code of verilog HDL for a street light. The LED on the board represent the green, yellow and red light.After some fixed time, the LED will be on or off for the command. Besides, the time will be count backwards, and it will be shown on the screen of the  board. It is very...
  verilog      Verilog     

Four lights switch of marquee (marquee program in verilog_hdl languages)

This is a learning verilog HDL good information, suitable for beginners, explained in detail, from the light into the deep, learning the language, it is a hardware description language for good stuff, good material!...
  verilog      Verilog     

verilog simulation filters

verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

SPI flash model written by verilog

M25Pxx ST company SPI flash memory verilog simulation model, the model correctly describes the behavior of SPI flash memory, including reading, writing and erase operations, can be used to hang outside of the SOC with SPI interface, verify that the SPI interface....
  verilog      Verilog     

Ledbanner in verilog code using FPGA SPARTAN-3E

Ledbanner in verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.  It will go from left to rigth or vise versa. And will reset fuction when press reset botton....
  verilog      Verilog     

verilog serial program based on ep4ce22

verilog circuits string mouth procedure based on ep4ce22, you can send 24bit, hoping to provide help....
  verilog      Verilog     

verilog uart 115200

Using serial port UART transmission module written in verilog, sending rate to 115200, input clock for 50m for many years validation without errors...
  verilog      Verilog     

verilog Code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....
  verilog      VHDL     

verilog design water lights

Under water lights in the verilog language module Design. Are the clock pulses + counters +LED control...
  verilog      Verilog     

verilog temperature control commands

verilog temperature control command realizes the temperature acquisition and operation, as well as other control  commands very well...
  verilog      Verilog     

AXI slave verilog code

Wrote AXI slaver verilog code, hope to give you some inspiration...
  verilog      Verilog     

shifter verilog

Here is shifter for verilog The structural generic approach for a barrel shifter needs a generate block. The for loop in the generate block will unravel at compile time, not run time like a for loop like in an always block. To keep it generic also have have the 2-to-1 mux ha...
  verilog      Verilog     

code verilog cordic core

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details...
  verilog      Verilog     

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