Sponsored links

Top Source Codes

Blif2vhdl format conversion tool

A BLIF to vhdl converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

Realization virtual electric piano based on vhdl

This program design using vhdl language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...
  vhdl      VHDL     

Waveform generator and sine waveforms generator based on vhdl language

Waveform generator and sine waveforms generator based on vhdl language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to vhdl is also helpful to-This i...
  vhdl      VHDL     

Wavelet transform and vhdl

Wavelet transform in JPEG2000 part of the vhdl source code. JPEG2000 The core algorithm is based on Discrete Wavelet transform. Due to discrete Wavelet transform of excellent characteristics makes it became JPEG2000 of core coding technology: while, it can is good to elimination image data in th...
  vhdl      VHDL     

FPGA60 binary digital tube display vhdl code

FPGA design 60 binary counter, through 2 seven-segment digital tube that is out. Code is straightforward, emulation through, loaded on the FPGA Development Board and show success. Useful codes to get started....
  vhdl      VHDL     

verilog and vhdl files

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port( clk: in std_logic; rst: in std_logic; q1: out std_logic); end tff1; architecture behavioral of tff1 is signal q: std_logic; begin process(clk,rst) begin...
  vhdl      VHDL     

Discrete Cosine Transform(DCT/IDCT) in vhdl

the Project aim is to design DCT and IDCT in vhdl. DCT is used in image compression to compress the JPEG image. This file contains DCT and IDCT blocks and top module which integrates two blocks and testbench to test the two modules....
  vhdl      VHDL     

vhdl code for latch_ff_comb for d_comb ckt in vhdl

library ieee; use ieee.std_logic_1164.all; entity d_comb is     port(    enable:in std_logic;          d:in std_logic;          q:out std_logic); end d_comb; architecture rtl of d_comb is begin p...
  vhdl      VHDL     

vhdl simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several parts through QuartusII 9 compiler testing is feasible. Code original containing syste...
  vhdl      VHDL     

vhdl for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
  vhdl      VHDL     

Learn vhdl displays a six-digit

During the eight-digit seven-segment digital display control display on 8-bit 学号 , To display the 的 学号 You can ride Sequence changes, device validation error-free and running well....
  vhdl      VHDL     

vhdl4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you start answering as a violation vie, violation vie warns players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...
  vhdl      VHDL     

vhdl code for different adders

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- hi...
  vhdl      VHDL     

I2CvhdlASDASDADASD

Content is too short. Attention please: Codes without good description will be deleted and you won't get any points. Please describe it better to get more points....
  vhdl      VHDL     

Image processing vhdl

XAPP928, you can refer to the study. which contains the color temperature adjustment, GAMMA adjustment, as well as spatial dithering algorithm for enhanced gray scale, these 3 basic image preprocessing algorithm is now commonly used flat panel display devices....
  vhdl      VHDL     

vhdl realization 8051 (full version)

vhdl realization 8051 (full version)...
  Algorithm      VHDL     

vhdl separator

vhdl PRograming its un aplicative tha it's performing at the memory ram  32 x 32 at rom 64 x 48...
  Windows      VHDL     

Ebcdic v.1.0

Component that converts strings ASCII for EbcdIC and EbcdIC for ASCII....
  Component        Delphi     

car racing_vhdl

This code is a car racing program in vhdl which is developed using xilinx spatan 3e board. This code is developed on the EDK platform, It has following modules 1. Buttons_4bit 2. Clock Generator 3. Debug module EDK is a emebedded development kit plaform from xili...
  Embeded      VHDL     

H264 motion estimation in vhdl

H264 estimation algorithms, vhdl description, detailed Readme document from github. FPGA and SOC can have a try....
  Algorithm      VHDL     

Hot Search Keywords


    Sponsored links
klatt synthesis matlab code |  asp pop |  rx12864 powered by TPK Guestbook the?cmd=sign < a <!doctyp |  deblur KSVD Powered by: Maian Guestbook myself:?mop=AddEnt |  deblur KSVD Powered by: Maian Guestbook myself:?cmd=sign |  deblur KSVD Powered by: Maian Guestbook myself: |  human expression detection |  韩国身份證 生成器id=374338532385h 0& prev= searchhBd |  stm32f4 Powered by: Maian Guestbook were?cmd=sign |  stm32f4 Powered by: Maian Guestbook were?mop=AddEntry&op=m |  stm32f4 Powered by: Maian Guestbook were?name=Gue hit 46 |  wlscgen |  modbus rtu ocx Designer: PHPLD Templates Submit Article |  stm32f4 Powered by: Maian Guestbook were |  criminisi Designer: Free PHPLD Templates Submit Article?c |  stm32 hd44780?mop=AddEntry&op=modload&name=Guest hit hit 8 h |  stm32 hd44780 |  C code microblaze processor |  real time video tracking in matlab |  online doctor appointment system |  online doctor appointment system?mop=AddEntry&op=modload&nam |  order dithering verilog |  音乐处理 c |  音效开源库 |  adaboost algorithm matlab code Sign the Guestbook: microseco |  ADI 2d heat equation |  sph cuda?1364136043 |  pareto front Powered by: Maian Guestbook absolute?cmd=sign |  major project |  neural network blood transfusion |  magnetometer in simulin |  opc |  fdtd 2d te pml fortran |  93cl86?name=Gu hit 347 href= s 0 business? hit 4372 href= |  object identification from image |  newton interpolation in scilab?mop=AddEntry&op=modload&name= |  newton interpolation in scilab |  defprmed |  Altera DE2 Synthesizer |  vocenhancer game by niit?bd cpro prev= |  excel addin using article directory plugin ?section=add |  JustinIO Powered by PHPLD Add Article أرم%2 RK=0 |  fast dtw matlab powered by Simple Machines?name=Guestbook |  Levenberg Marquardt Algorithm matlab |  sc fdma ber vs snr matlab |  openmp minimum spanning tree |  流控 uart “Using Article Directory plugin”??mop=AddEnt |  image annotation matlab code |  Mstar 7816 4?mop=AddEntry&op=modload&name=Guest hit hit 8 h  |  雷达成像之RD算法 |  ??? Using Article Directory plugin |  GUESTBOOK asp inurl:as p?action=sign moose? ct=clnk |  ADS1294 texas Powered by: php Link Directory Add Article? |  AT91sam9260 GPIO驱动 linux |  Mstar 7816 4 |  M bus?mop=AddEntry&op=modload&name=Guest hit hit 8 h h hit 1 |  book management |  pic 12F675 74hc595 pwm controller?mop=AddEntry&op=modload&n |  pic 12F675 74hc595 pwm controller |  ADS1294 texas Powered by: php Link Directory Add Article |  pdf2word Powered |  Ammyy Admin?mop=AddEntry&op=modload&name=Guest hit hit 8 h h |  h264 DE2 uClinux |  iq test RK=0 RS=jjwGVlCB7OzofMHP8p7kxh4jIxE |  LPC21 i2C?cmd=sign |  lpc2103 |  LPC2102 |  criminisi Designer: Free PHPLD Templates Submit Article?m |  Ammyy Admin |  ?mop=AddEntry&op=modload&name=Guest hit hit 8 h h hit hit 1 |  远程XML接口提交数据 |  multi level cell flash in verilog?cmd=sign |  xilinx IP core decrypt modules mod ppc simple spotlight el |  Defrag Memory powered by TPK Guestbook thereby |  pie chart opengl |  ????????? Ultimate Guestbook Version |  gradıent |  vampire attack adhoc sensor network ns2 coding?mop=AddEntr |  labview usbraw |  vampire attack adhoc sensor network ns2 coding |  SBC8600B Designed by: PHPLD Your Site Add Article word |  none |  sph algorithm |  plotseis?mop=AddEntry&op=modload&name=Guest hit hit 8 h h hi |  multi level cell flash in verilog?mop=AddEntry&op=modload&na |  s3c2410 code example |  s3c2410 sdi driver |  ear recognition using matlab |  s3c2410 sdi drivers?mop=AddEntry&op=modload&name=h hi hit 1 |  Affine hill cipher |  FPGA based CAN Bus Controller design using Verilog VHDL?mop= |  gps module Designed by: PHPLD Your Site Submit Article?mo |  GSM voice call simulation in matlab |  Speech coding using hmm |  gps module Designed by: PHPLD Your Site Submit Article |  FPGA based CAN Bus Controller design using Verilog VHDL |  stepper motor speed controle usb for medical |  tabu search matlab codes?mop=AddEntry&op=modload&name=Guest |  punkbuster |  template for iris recognition |