Sponsored links

Top Source Codes

Blif2vhdl format conversion tool

A BLIF to vhdl converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

Rs232 using vhdl

Disign RS232 controller using vhdl on Altera DE2. This is a serial module which is useful for embed systems....
  vhdl      VHDL     

Wavelet transform and vhdl

Wavelet transform in JPEG2000 part of the vhdl source code. JPEG2000 The core algorithm is based on Discrete Wavelet transform. Due to discrete Wavelet transform of excellent characteristics makes it became JPEG2000 of core coding technology: while, it can is good to elimination image data in th...
  vhdl      VHDL     

Waveform generator and sine waveforms generator based on vhdl language

Waveform generator and sine waveforms generator based on vhdl language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to vhdl is also helpful to-This i...
  vhdl      VHDL     

Realization virtual electric piano based on vhdl

This program design using vhdl language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...
  vhdl      VHDL     

Learn vhdl displays a six-digit

During the eight-digit seven-segment digital display control display on 8-bit 学号 , To display the 的 学号 You can ride Sequence changes, device validation error-Free and running well....
  vhdl      VHDL     

vhdl for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
  vhdl      VHDL     

verilog and vhdl files

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port( clk: in std_logic; rst: in std_logic; q1: out std_logic); end tff1; architecture behavioral of tff1 is signal q: std_logic; begin process(clk,rst) begin...
  vhdl      VHDL     

Discrete Cosine Transform(DCT/IDCT) in vhdl

the Project aim is to design DCT and IDCT in vhdl. DCT is used in image compression to compress the JPEG image. This file contains DCT and IDCT blocks and top module which integrates two blocks and testbench to test the two modules....
  vhdl      VHDL     

vhdl code for latch_ff_comb for d_comb ckt in vhdl

library ieee; use ieee.std_logic_1164.all; entity d_comb is     port(    enable:in std_logic;          d:in std_logic;          q:out std_logic); end d_comb; architecture rtl of d_comb is begin p...
  vhdl      VHDL     

vhdl simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several parts through QuartusII 9 compiler testing is feasible. Code original containing syste...
  vhdl      VHDL     

FPGA60 binary digital tube display vhdl code

FPGA design 60 binary counter, through 2 seven-segment digital tube that is out. Code is straightforward, emulation through, loaded on the FPGA Development Board and show success. Useful codes to get started....
  vhdl      VHDL     

vhdl4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you start answering as a violation vie, violation vie warns players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...
  vhdl      VHDL     

vhdl code for different adders

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- hi...
  vhdl      VHDL     

I2CvhdlASDASDADASD

Content is too short. Attention please: Codes without good description will be deleted and you won't get any points. Please describe it better to get more points....
  vhdl      VHDL     

Image processing vhdl

XAPP928, you can refer to the study. which contains the color temperature adjustment, GAMMA adjustment, as well as spatial dithering algorithm for enhanced gray scale, these 3 basic image preprocessing algorithm is now commonly used flat panel display devices....
  vhdl      VHDL     

vhdl realization 8051 (full version)

vhdl realization 8051 (full version)...
  Algorithm      VHDL     

ABySS Web Server

AByss used to have a socket concept modelled after POSIX sockets, in which a single class (TSocket) contained two very different kinds of objects:  some analogous to a TChanSwitch and analogout to a TChannel. Now that we have TChanSwitch and TChannel, users should use those,&nb...
  Socket        C++     

FreeModbus study notes

FreeModbus study notes A profile of FreeModbus, FreeMODBUS Austria written By Modbus Protocol. It is an embedded application of a Free (Free) generic MODBUS Protocol in mind. Modbus is an industrial manufacturing environment for the adoption of a common Tweet. Modbus communication protocol stack...
  Embeded        C     

vhdl separator

vhdl PRograming its un aplicative tha it's performing at the memory ram  32 x 32 at rom 64 x 48...
  Windows      VHDL     

Hot Search Keywords


    Sponsored links
tmp112 tiny?name=Guestbook?mode=register&agreed=true&iscanye |  基于bessel函数的恒定束宽波束形成 |  RECONNAISSANCE DES CHIFRES PAR CORR2LATION |  dsniffer Powered by Advanced Guestbook Black?mop=AddEntry& |  UDA1380 驱动?cmd=sign?name=Guestbo hit 10931 href= hit 3 h |  matlab code for planar irregular rectangular subarrays to r |  使输出滚动 |  ofdm 澶氬緞 |  artificial bee colony implementation |  VC ??WORD????? |  Arithmetic decoding |  AUTO TLBB |  TDSC |  psytec QR |  c txt数据文件读取 |  SPI VERILOG Using Article Directory plugin encipher&ct=cln |  6410 裸机 Powered by Easy Guestbook ddys? c |  first and follow set in compiler?mop=AddEntry&op=modload&nam |  sqlite odbc |  6410 裸机 Powered by Easy Guestbook ddys& c?mop=AddEn |  cc2430 解调 |  opencv on ARM |  uart read write windows |  即时通讯 android |  SAM3S EK Ultimate Guestbook Version danmark?name=hit hit |  Evtx Parser Powered by Easy Guestbook thefts?cmd=sign?cmd? |  心电 arm |  modbus atmega Powered by Advanced Guestbook |  b spline openCV powered by Simple Machines oblong?name=hit |  【力天电子】 第十四讲 |  first and follow set in compiler?mop=AddEntry?op=modload&nam |  bfflime RK=0 |  um2460 |  shape from shading matlab source code fo |  vb for windows xp Ultimate Guestbook Version?name=Guestboo |  RLE? Powered by Advanced Guestbook Powered?cmd=sign?cmd=si |  number xml?cmd=sign |  鑰佸鐨勪唬鐮? |  成都国嵌 |  pacman 8086 powered by advanced guestbook pea?mop=AddEntry |  2812 spi eeprom Powered by Advanced Guestbook tape? ct= |  ?? 2D 3D Powered by Advanced Guestbook amb?cmd=sign?cmd=si |  motion vector field Powered by Advanced Guestbook balloon |  TDMA solver in c |  ds1307 and f410 |  储油罐容积和高度的关系?cmd=sign?cmd=sign |  jwellory shopping |  Metal Slug Powered by Easy Guestbook reiterated&ct=clnk RK |  sd鍗 dma |  SPI VERILOG Using Article Directory plugin encipher??cmd=s |  MSP mic |  dtree in matlab download |  LPC17xx 24c02 |  广告点阵屏 |  stopwatch in verilog with milliseconds |  T6963C driver |  usb str710 |  matlab str2hex |  PL 缂栬瘧鍣? |  c#姘稿畯plc |  ShowRadarData |  jsp考试系统B S |  三维重建示例可演示 |  image warping Powered by Advanced Guestbook freely&ct=?mop |  &#27603 Powered By: Article Friendly Ultimate &#2 |  Hook keyboard MFC |  鑴辨満澶栨寕鏄撹瑷€ |  Windows minidriver |  鑷洖褰掑垎鏋 |  uip enc28j60 stm32 webclient |  OPENGL小溪 |  ADS?ARM Linker |  缂栫▼瀹炵幇瀵圭墿鐞嗙殑骞宠鎶曞奖 |  vce pro powered by advanced guestbook thinly?mop=AddEntry |  P33FJ256GP710A |  屏幕和语音广播 C |  小车 vc |  网吧管理系统网站 c |  教研室管理系统 |  粒子群优化算法优化神经网络?did=ca454caa93201158 |  闅忔満杩愬姩妯″瀷 |  D3DFMT a16b16g16r16f |  粒子群优化算法优化神经网络&did=ca454caa93201158 |  digital audio watermarking using matlab |  dynamic stability |  DEC642 boot |  简单的地理信息系统C |  安卓超级终端df部件?did=ca454caa93201158 c37887353fb8 |  WinHttpOpenRequest |  might |  solomon ssd1963 Powered by: Maian Guestbook only?name=Gu h |  8queen genetic algorithm |  lotus开发的珠海区政府OA程序 |  鍥惧儚 璇樊 瀵规瘮 鏁板 |  基于MAS的垃圾邮件检测系统的设计与实现 |  鏉$爜瀛椾綋OCR B |  XML动态创建对话框 |  QT瀹炰緥 |  assa外挂 powered by TPK Guestbook immunity&c?mop=AddEntr |  报到系统 |