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Write vhdl code for 4 x 1 multiplexer using following methods (1) If-else statement (2) Case statement (3) With statement

Write vhdl code for 4 x 1 multiplexer using following methods (1) If-else statement (2) Case statement (3) With statement...
  vhdl      VHDL     

FPGA60 binary digital tube display vhdl code

FPGA design 60 binary counter, through 2 seven-segment digital tube that is out. code is straightforward, emulation through, loaded on the FPGA Development Board and show success. Useful codes to get started....
  vhdl      VHDL     

vhdl code for latch_ff_comb for d_comb ckt in vhdl

library ieee; use ieee.std_logic_1164.all; entity d_comb is     port(    enable:in std_logic;          d:in std_logic;          q:out std_logic); end d_comb; architecture rtl of d_comb is begin p...
  vhdl      VHDL     

vhdl code for different adders

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- hi...
  vhdl      VHDL     

cache memory

This code is the code cache, using the least recently used algorithm. Roughly 1000-2000 lines of code, the program includes cache replacement algorithm implementations. Selection of image rules, as well as all of the simulations....
  verilog      Verilog     

vhdl code for Adder / Subtractor

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY adder IS PORT(Cin        : IN STD_LOGIC; Carry        : IN STD_LOGIC;  X,Y        : IN STD_LOGIC_VE...
  Matlab      VHDL     

RSA vhdl code

Here, we present the first available open-source 512 bit RSA core. This is an early prototype version of a full FIPS Certified 512-4096 capable RSA Crypto-core which will be on sale soon. The version provided, has not the same performance than the final product since it was a proof of concept tha...
  verilog      Verilog     

Adder in vhdl

This program is an  adder for two floating numbers using vhdl language....
  vhdl      VHDL     

Blif2vhdl format conversion tool

A BLIF to vhdl converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

Rs232 using vhdl

Disign RS232 controller using vhdl on Altera DE2. This is a serial module which is useful for embed systems....
  vhdl      VHDL     

vhdl frequency meter

Using the frequency meter vhdl write and modules divided into clear, basic principles for the detection of pulse signals in the life cycle of a gate frequency, use the four-segment digital tube display...
  vhdl      VHDL     

Fast Vedic Mathematic Multiplication using vhdl

This document contains the detail contents for the vedic multiplier in vhdl. It contents the detial explaination of the vedic multiplier process....
  vhdl      VHDL     

Realization virtual electric piano based on vhdl

This program design using vhdl language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...
  vhdl      VHDL     

vhdl simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several parts through QuartusII 9 compiler testing is feasible. code original containing syste...
  vhdl      VHDL     

vhdl code for counter

Here is the code for counter in vhdl. --signal slow_clk : std_logic := '0';  --signal clk_divider : std_logic_vector(23 downto 0) := x"000000"; -- Clock divider can be changed to suit application.  -- Clock (clk) is normally 50 MHz, so each clock cycle  -- is 20 ns. A clock...
  vhdl      VHDL     

Radix-8 Booth Encoded Modulo

vhdl code for Radix-8 Booth Encoded Module  Multipliers With Adaptive Delay for High Dynamic Range Residue Number System...
  vhdl      VHDL     

Wavelet transform and vhdl

Wavelet transform in JPEG2000 part of the vhdl source code. JPEG2000 The core algorithm is based on Discrete Wavelet transform. Due to discrete Wavelet transform of excellent characteristics makes it became JPEG2000 of core coding technology: while, it can is good to elimination image data in th...
  vhdl      VHDL     

vhdl code for 8*1 mux design

vhdl code for 8*1 mux design library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;     entity counter is     Port ( clk : in  STD_LOGIC...
  vhdl      VHDL     

Discrete Cosine Transform(DCT/IDCT) in vhdl

the Project aim is to design DCT and IDCT in vhdl. DCT is used in image compression to compress the JPEG image. This file contains DCT and IDCT blocks and top module which integrates two blocks and testbench to test the two modules....
  vhdl      VHDL     

Waveform generator and sine waveforms generator based on vhdl language

Waveform generator and sine waveforms generator based on vhdl language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to vhdl is also helpful to-This i...
  vhdl      VHDL     

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