Sponsored links

Top Source Codes

FPGA60 binary digital tube display vhdl code

FPGA design 60 binary counter, through 2 seven-segment digital tube that is out. code is straightforward, emulation through, loaded on the FPGA Development Board and show success. Useful codes to get started....
  vhdl      VHDL     

vhdl code for latch_ff_comb for d_comb ckt in vhdl

library ieee; use ieee.std_logic_1164.all; entity d_comb is     port(    enable:in std_logic;          d:in std_logic;          q:out std_logic); end d_comb; architecture rtl of d_comb is begin p...
  vhdl      VHDL     

vhdl code for different adders

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- hi...
  vhdl      VHDL     

Soda machine vending machine

vending machine based on spartan6 prepared from digital design with computer architecture project. Mobile Information Engineering College of Zhongshan University curriculum practice, this code can provide a reference for everyone. This source press input, four seven-segment decoder display current a...
  verilog      Verilog     

vhdl code for Adder / Subtractor

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY adder IS PORT(Cin        : IN STD_LOGIC; Carry        : IN STD_LOGIC;  X,Y        : IN STD_LOGIC_VE...
  Matlab      VHDL     

RSA vhdl code

Here, we present the first available open-source 512 bit RSA core. This is an early prototype version of a full FIPS Certified 512-4096 capable RSA Crypto-core which will be on sale soon. The version provided, has not the same performance than the final product since it was a proof of concept tha...
  verilog      Verilog     

Blif2vhdl format conversion tool

A BLIF to vhdl converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

Rs232 using vhdl

Disign RS232 controller using vhdl on Altera DE2. This is a serial module which is useful for embed systems....
  vhdl      VHDL     

vhdl simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several parts through QuartusII 9 compiler testing is feasible. code original containing syste...
  vhdl      VHDL     

Realization virtual electric piano based on vhdl

This program design using vhdl language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...
  vhdl      VHDL     

vhdl code for counter

Here is the code for counter in vhdl. --signal slow_clk : std_logic := '0';  --signal clk_divider : std_logic_vector(23 downto 0) := x"000000"; -- Clock divider can be changed to suit application.  -- Clock (clk) is normally 50 MHz, so each clock cycle  -- is 20 ns. A clock...
  vhdl      VHDL     

Wavelet transform and vhdl

Wavelet transform in JPEG2000 part of the vhdl source code. JPEG2000 The core algorithm is based on Discrete Wavelet transform. Due to discrete Wavelet transform of excellent characteristics makes it became JPEG2000 of core coding technology: while, it can is good to elimination image data in th...
  vhdl      VHDL     

Radix-8 Booth Encoded Modulo

vhdl code for Radix-8 Booth Encoded Module  Multipliers With Adaptive Delay for High Dynamic Range Residue Number System...
  vhdl      VHDL     

Discrete Cosine Transform(DCT/IDCT) in vhdl

the Project aim is to design DCT and IDCT in vhdl. DCT is used in image compression to compress the JPEG image. This file contains DCT and IDCT blocks and top module which integrates two blocks and testbench to test the two modules....
  vhdl      VHDL     

Waveform generator and sine waveforms generator based on vhdl language

Waveform generator and sine waveforms generator based on vhdl language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to vhdl is also helpful to-This i...
  vhdl      VHDL     

ADC vhdl code

Using VHDI Dispaly character. shows a simulation of a properly working implementation of LCD controller hardware. This simulation demonstrates the way the disparate state machines work together. As the initialization sequence finishes, the command states of the main state machine begin....
  vhdl      VHDL     

vhdl code for multiplexer

vhdl program for multiplexer we can write 4:1 mux also like this its very simple code for beginers to understand...
  vhdl      VHDL     

verilog and vhdl files

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port( clk: in std_logic; rst: in std_logic; q1: out std_logic); end tff1; architecture behavioral of tff1 is signal q: std_logic; begin process(clk,rst) begin...
  vhdl      VHDL     

I2CvhdlASDASDADASD

Content is too short. Attention please: codes without good description will be deleted and you won't get any points. Please describe it better to get more points....
  vhdl      VHDL     

vhdl code for fulladder of Behavioral Model

TOOLS   REQUIRED               Simulation tool: modelsim or Xilink PROCEDURE 1. To start the programs click the modelsim software. 2. The main page is opened,click the file option to crea...
  vhdl      VHDL     

Hot Search Keywords


    Sponsored links
dreambox jtag?mop=AddEntry&op=modload&name=Guestbook&file=in |  ChnCalendarPicker Designer: PHPLD Templates Add Article?c |  compatibility function in matlab |  MATLAB IIR滤波 |  4x4 keypad matrix LPC2148 |  automatic door machine |  histogram matching matlab |  16f877 2 digit 7segment c code |  Binomial Smooting |  vfp 透明flash |  3d anaglyph?cmd=sign |  permuatation?mop=AddEntry&op=modload&name=Guest h? hit 1 hr |  8x8 led matrix LPC2138 |  A star Algorithm c |  ns2 GPRS code?mop=AddEntry&op=modload&name=G hit 6 hit 1 hr |  ? Powered by Advanced Guestbook&sa=U |  CiITxCffoDn |  NTfs代码 |  ?mop=AddEntry&name=Guestb hit 10 href= h hit 18&op=modload |  online shopping project jsp servlet mysql |  中文分词 perl |  a b?? |  s3c2440 AC97 Powered by: php Link Directory Add Article |  image segmentation split merge matlab |  ? Powered By: Article Friendly Ultimate ? |  c pascal converter |  fractal inter |  webmin cccam Designed by: PHPLD Your Site Submit Article |  Digital Signal Processing Mini Project using matlab |  proteus pcb |  adaboost lpr Designed by: PHPLD Your Site Submit Article |  RGB888 YUV Designed by: PHPLD Your Site Submit Article?mo |  xnxx powered?mop=AddEntry&op=modload&name=Guestbook&file=in |  FUZZY MCDM?mop=AddEntry&op=modload&name=Guestbo hit 18 href |  Rc4 MAPLE in Designed by: PHPLD Your Site Add Article |  ucos2 lpc2148 mp3 player |  CT matlab |  histogram equalization code in opencv |  online admission system in jsp |  s3c2440 AC97 Powered by: php Link Directory Add Article?m |  s?amp&p Rate this Article : Current : 96 RK=0 RS=aCrFikoNj |  LPC2148 serial proteus |  devicenet Designed by: PHPLD Your Site Submit Article? p |  5509 mcbsp spi Powered by Easy Guestbook denser?cmd=si |  devicenet Designed by: PHPLD Your Site Submit Article ?&c? |  xnxx powered |  devicenet Designed by: PHPLD Your Site Submit Article ?act |  raw dicom |  xnxx powered?cmd=sign |  business object?cmd=sign?name=Guestbook Enter the ca?c?cmd=s |  vce pro powered by advanced guestbook thinly?mop=AddEntry |  CSharp pacman |  mpeg2dec |  8 puzzle a star?cmd=sign |  osgRiver Designer: Free PHPLD Templates Submit Article w |  4bit counter |  force directed graph |  89s51 24c02 |  STM8 orcad Add Article PHP Link Directory ?ct=clnk |  optical fiber communications by gerd keiser solution manual |  FFVCL Encode|4 Powered by: Maian Guestbook encoders&ct=c?n |  8 puzzle with hill climber |  三æ˜ÿ 2416 ucos |  1 Z |  html |  json struts |  Turbo Pascal |  RTCP Designed by: PHPLD Your Site Submit Article packa?c |  spartan 3e xc3s500e sch |  Skill Builder: Turtle Maze Skill Builder: Defining Nested |  osg Shp Designed by: PHPLD Your Site Submit Article expe |  vlsi mini projects based on verilog or vhdl |  Tsvm Designed by: PHPLD Your Site Submit Article input&c |  gui speech recognition viterbi hmm?name=guestbook | | |  OpenCV CBIR powered by TPK Guestbook cardio?name=Gu hit? h |  MJPeG JPG Powered by Advanced Guestbook ends?name=Gu hit? |  Online library management system mini project IN JSP |  嵌入 应用程序 |  bi cubic spline interpolation?mop=AddEntry&op=modload&name=G |  homebus鍗忚?mop=AddEntry&op=modload&name=Gues hit 4 hr |  objective c rtp |  CodeNGen |  coint enter word verification in box below guestbook&prev= |  Job Shop genetic |  psnr mse in matlab?agreed=true&iscanyesno=yesw&mode=register |  bi cubic spline interpolation |  image segmentation using split and merge method in matlab |  bi cubic spline interpolation?cmd=sign |  jain sip server?file&mop=AddEntry&name=Guestbook&op=modload |  coint enter word verification in box below guestbook?prev= |  henon map for encryption image |  skeleton ? Powered by Advanced Guestbook mandate= 1 &=amp? |  s 5 blogs load recent inurl: blogs load recent arm&ct=cl?n |  Algorithm?mop=AddEntry&name=guestbook hi h hit 57&op=modload |  android IP cam |  easy hid。zip?action=add |  ?mop=AddEntry&op=modload&name=guestbook h hit 134 hit 2802 |  Other Books ? zb path=test?amp sa=U&amp ei=tlhhUar1B8jZ4QT |  撋憡?mode=register&agreed=true&iscanyesno=yesw |  fuzzify谋ng 谋nputs |