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vhdl realization 8051 (full version)

vhdl realization 8051 (full version)...
  Algorithm      VHDL     

vhdl obtaining quadrature

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; Library UNISIM; use UNISIM.vcomponents.all; --------------------------------------------------------------------...
  signal Processing      VHDL     

Using FPGA verilog HDL simulation class I2C communication

Using FPGA verilog HDL simulation class I2C communication...
  verilog      Verilog     

digital to analog convertor using vhdl ams

Its a project baded on implementing digital to analog convertor using vhdl-AMS using behavourial as well as structural abstractions....
  vhdl      VHDL     

An implementation of a Fault Detection and Isolation System on Foundation Fieldbus Environment

This work shows an implementation of a fault detection and isolation (FDI) system applied to a levels control system. The levels system is connected to a Foundation Fieldbus industrial network. The FDI system was developed using artificial neural networks and tested just as much in simulated en...
  Data        PPT     

GOF design patterns Lexi text editor in the Delphi implementation

Lexi in the Delphi implementation of the GOF design patterns text editor...
  设计模式        Delphi     

16 bit risc processor for computer hardware

16 bit risc processor for computer hardware ...
  Algorithm      VHDL     

Gaosilerangde C++ implementation of integral algorithm

Gaosilerangde integral algorithms C++ implementation, using Gauss algorithm for 10 points here, have a high efficiency and precision...
  Algorithm        C++     

MFC implementation snake

Prepared under the snake with a simple MFC dialog box, use the simplest technology approaches to make, with source code, produced mainly in order to study drawing and other related approaches....
  Windows        C++     

Remove Noise of the kmeans algorithm, Java implementation

Nothing says, directly on the source code...
  数据挖掘算法        Java     

Backpack zero-first Java implementation

import java.util.Scanner; public class Packsack{ Scanner sc=new Scanner(System.in); Int n;//number of items Int m;//bag maximum capacity Int w[];//stores the weight of each item Int v[];//stored value of each item Int Max[][];//Bank said first I items, list capacity j, the values for I...
  算法        Java     

MATLAB implementation of DMC algorithm

DMC predictive control algorithm to achieve results....
  Matlab        Matlab     

Countdown clock

vhdl countdown clock, Countdown to A,B at the same time, the LCD display...
  sock      VHDL     

FSMD with reg,mux,fib

An FSMD impemented in vhdl, with a mux,reg,fib function, tested on xilinx ide and implemented into fpga...
  Embeded      VHDL     

Counter Impl sp605

A counter implementation for sp605 xilinx board...
  Embeded      VHDL     

Error detection code

error detection code error detection code with cyclic redundancy coding codigo detector de errores código detector de errores con codificación de redundancia ciclica...
  Windows        Matlab     

Adder Subber xilinx fpga sp605

Adder/subber project for xilinx fpga sp605...
  Embeded      VHDL     

High

High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard...
  VHDL-FPGA-Verilog        Others     

82 vhdl, verilog test case, involving a variety of grammatical rules. which is...

82 vhdl, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper....
  VHDL-FPGA-Verilog      VHDL     

RFC1662 crc

RFC1662 crc-16 table generation and crc checking. Implemented in embedded matlab with script to test and enable c/c++ code generation. Useful fo check against vhdl/verilog and other embedded systems to help generate test vectors....
  matlab        Matlab