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vhdl for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
  vhdl      VHDL     

vhdl frequency meter

Using the frequency meter vhdl write and modules divided into clear, basic principles for the detection of pulse signals in the life cycle of a gate frequency, use the four-segment digital tube display...
  vhdl      VHDL     

Selfish node detection using Dsr

Selfish node detection using  Dsr protocol in  mobile adhoc wireless simulation.here we creat 4 selfish nodes and totals nodes are 20. this topology is 500*500 and uses random way point mobility model....
  Linux programming      Tcl/Tk     

Blif2vhdl format conversion tool

A BLIF to vhdl converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

Rs232 using vhdl

Disign RS232 controller using vhdl on Altera DE2. This is a serial module which is useful for embed systems....
  vhdl      VHDL     

script-olsr-etx

olsr routing protocol  behavior for Ad hoc networks with multiple traffic types that implemented in ns2 network simulator....
  Linux programming      Tcl/Tk     

Latches, flip-flops, and Registers - DE2-115

The purpose of this exercise is to investigate latches, flip-flops, and registers....
  vhdl      VHDL     

vhdl code for latch_ff_comb for d_comb ckt in vhdl

library ieee; use ieee.std_logic_1164.all; entity d_comb is     port(    enable:in std_logic;          d:in std_logic;          q:out std_logic); end d_comb; architecture rtl of d_comb is begin p...
  vhdl      VHDL     

vhdl simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several parts through QuartusII 9 compiler testing is feasible. code original containing syste...
  vhdl      VHDL     

Wavelet transform and vhdl

Wavelet transform in JPEG2000 part of the vhdl source code. JPEG2000 The core algorithm is based on Discrete Wavelet transform. Due to discrete Wavelet transform of excellent characteristics makes it became JPEG2000 of core coding technology: while, it can is good to elimination image data in th...
  vhdl      VHDL     

Realization virtual electric piano based on vhdl

This program design using vhdl language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...
  vhdl      VHDL     

Gpsr source code

Gpsr source code, test files gpsr。 cc gpsr.h gpsr_neighbor.h gpsr_neighbor.cc gpsr_sinklist.h gpsr_sinklist.cc wireless-gpsr gpsr_packet...
  Linux programming        C++     

Discrete Cosine Transform(DCT/IDCT) in vhdl

the Project aim is to design DCT and IDCT in vhdl. DCT is used in image compression to compress the JPEG image. This file contains DCT and IDCT blocks and top module which integrates two blocks and testbench to test the two modules....
  vhdl      VHDL     

Waveform generator and sine waveforms generator based on vhdl language

Waveform generator and sine waveforms generator based on vhdl language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to vhdl is also helpful to-This i...
  vhdl      VHDL     

json_autocodegenerator

Json_autocodegenerator JSON code automatic generation tools you can automatically generate a JSON string parsing code...
  Linux programming        C     

Minidatabase

To implement your own database management program. You can write SQL statements in the input, then I can help you with the program statement, then the reaction in my database, my database, I manage storage, table properties are stored, and so on. To compliment my own buffer technology, of cour...
  DataBase        Visual C++     

turbo code on FPGA on vhdl

This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer....
  vhdl      VHDL     

or gATE with data flow

entity or_gate port(a,b:in std_logic;c:out std_logic); end or_gate; architecture dataflow of or_gate is begin c<=a or b; end dataflow;...
  vhdl      VHDL     

vhdl4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you start answering as a violation vie, violation vie warns players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...
  vhdl      VHDL     

Learn vhdl displays a six-digit

During the eight-digit seven-segment digital display control display on 8-bit 学号 , To display the 的 学号 You can ride Sequence changes, device validation error-free and running well....
  vhdl      VHDL     

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