Top Source Codes

Implementation of des algorithm

The most streamlined implementation of des algorithm, so that you can quickly understand the usage of des....
  Algorithm        Visual C++     

The triple des algorithm

Providing triple-des algorithm, including file encryption, decryption algorithm, the most explicit c code, you can directly use the code and implementation of data encryption and decryption...
  Algorithm        C     

des algorithm (C Source Code)

This is the des encryption algorithm  in C. Welcome to download and try. Thank you very much for your support!...
  Algorithm        C     

SOPC technology using verilog create Hello program

SOPC technology FPGA verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

des algorithm encryption

Simple des encryption algorithm c language code implementation, you can simple implementation but have a problem where the wrong do not know please help me see, wrote may not be complete, limited so please do bear with me....
  Algorithm        C     

Parallel in serial out using verilog

This simplied program simulates the parallel in serial out. Implemented on Altera board succesfully. in case parallel in serial out, the data is accepted serially and is outputted after certain number of clock cycles....
  verilog      Verilog     

des algorithm

des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des algorithm des al...
  Java Development        Java     

des algorithm, written in c++

Console program he wrote, not optimized, significantly more than 300 k per second or so. In accordance with the standard des algorithm design, for those who need to provide a reference. There is insufficient please correct me, thank you!!...
  Crack Hack        C++     

Full adder in verilog

A simple verilog code for full_adder. It is tested in both simulator and xilinx spartan3E fpga board. ...
  verilog      Verilog     

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...
  verilog      Verilog     

8 bit adder verilog

hey here is a ise format code for xilinx software verilog 8 bit fixed point coding use this for example for coding with test bench...
  verilog      Verilog     

des encryption algorithm

des encryption algorithms, C++ implementation. validated workable. Welcome to download and try. Thank you for your support....
  Algorithm        C++     

DDR2 controller, verilog source code

using verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...
  verilog      Verilog     

verilog implementation of cordic algorithm

CORDIC algorithm can be implemented through different forms of solving multiplication, Division, square root, and some  trigonometric functions Operational problems. These calculation of trigonometric functions is to use hardware is Not easy to attain, and the CORDIC algorithm can...
  verilog      Verilog     

Ledbanner in verilog code using FPGA SPARTAN-3E

Ledbanner in verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.  It will go from left to rigth or vise versa. And will reset fuction when press reset botton....
  verilog      Verilog     

verilog simulation filters

verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

verilog uart 115200

using serial port UART transmission module written in verilog, sending rate to 115200, input clock for 50m for many years validation without errors...
  verilog      Verilog     

Parallel CRC verilog code generator

A parllel CRC verilog generator has been written in C++ to generate a parallel CRC verilog code for a given user defined data width and CRC polynomial. This is from outputlogic.com . This a direct implementation algorithm used in the website....
  verilog      Verilog     

DDS_Dual_ports verilog implementation

DDS_Dual_ports verilog implementation, you need to download experiment, according to their own needs to be modified in order to achieve the purpose of its...
  verilog      Verilog     

verilog serial port serial port receive module receiver module

verilog serial port serial port receive module receiver module, contains the BPS modules, level detection module and the control module...
  verilog      Verilog     

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