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android clock

clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock, clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock, clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock,clock, clock,clock,clock,clo...
  Java Development        Java     

clock_Single_LED_ATMEGA8

This is my clock project. "clock single LED with ATMEGA8". Led7seg created by Single-LED. it's very beautiful and brilliant. in this project also decode SONY remote control features to set the hour....
  AVR micro Controler        C     

Matrix_clock_Atmega16

часы построен на Atmega16 , управления через IRDA, 8 будильники , два DS18B20 датчик температуры улица + дом , коррекция прогресс високосный год , дни недели и многое друго...
  Clock_matrix        C++     

linux下基于gtk+的即时通讯软件

此源代码是在linux环境系基于gtk+和mysql编写的即时通讯软件,可以实现基本的聊天功能、搜索添加好友、处理离线消息、文件传输、表情发送等功能....
  Linux programming        C     

基于gtk+的单词数值计算器-linux

基于gtk+的单词数值计算器-linux 华南农业大学大三linux课程综合实验...
  Linux programming      Shell     

VHDL and verilog implementation of clock 20 and 50 and 10 and 30 Mhz generation

fpga implemantaion of clock generation. if  i am working on 50 mhz clock generation i want to design clk counter with some clk 10mhz geneartion then what can i do for that one to implemneting 20mhz from 50mhz without using any ip core directly using coding tecniques we can imp...
  Windows      Verilog     

clock division in verilog

Test program for clock division by selected value (32 bits). Its write in Verilog for Altera QuartusII....
  verilog      Verilog     

Analog clock using WPF

Complete source code of WPF analog clock  ...
  CSharp        C#     

silverlight clock

silverlight clock c++;silverlight clock c++;silverlight clock c++;silverlight clock c++;silverlight clock c++;silverlight clock c++;...
  Other        C++     

89C51 1602 lcd clock

4 * 4 matrix keyboard , which is used to change the time of the clock.  1602LCD, which is used to display the time in a format of hour-minute-second/years-month-day. All of the components is controlled by the MCU of 89C 51. This project is simulated on the tools of p...
  proteus;keil        C     

Countdown clock

VHDL countdown clock, Countdown to A,B at the same time, the LCD display...
  sock      VHDL     

Digital clock Multisim

This is a clock created with multisim simulator.This is a clock created with multisim simulator.This is a clock created with multisim simulator.This is a clock created with multisim simulator.This is a clock created with multisim simulator.This is a clock created with multisim simulator.This is a cl...
  Multimedia        Others     

clock Generator

This is a project that generate clock using pll. This project is programmed by VHDL. With plls, we can generate any clock for systems. That is so useful for IP core design....
  vhdl      VHDL     

REAL TIME clock BY 8051

This is a simple code of digital clock using 8051. Welcome download and try. Thank you for your support....
  Embeded        C     

clock with animated digits from PNG file with Alpha

Digital clock with skinned digits loaded from PNG file with alpha channel support. It uses zlib, pngimage and pngextra library in Delphi language....
  Image Processing        Delphi     

fifo_seperate_clock

It is a normal fifo programing code. where both Read and Write clock are different. for writing process  reading process seperate pointers used and for controling both process 3 additional pointers are used 1 pointer for write pointer control other for read pointer...
  vhdl      VHDL     

Digital-Analog clock in Java

//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ //#########################-----Created by SAJIB MITRA (ROCKY) //#########################-----Batch: 11th,SEASON: 2005-06 //#########################-----DEPT:  COMPUTER SCIENCE & ENGINEERING //#########################-----UNIVERSITY: &nb...
  Java Development        Java     

Digital clock based on Verilog

Here it is a verilog code for digital clock with alarm where you can set alarm time. It's a full working code. It's developed on vertex platform. So first do you configuration according to the code ....
  Embeded      Verilog     

NIXIE tube clock

8 digital stopwatch clock implementation, FPGA using EP2C80208C8N through digital tube carrying module the control module, the chronograph module, clock for accurate timing....
  vhdl      VHDL     

MFC clock alarm clock features double buffering

Under VC6.0 MFC write clock, the clock counts drawn using double buffering, alarm function, can be scheduled. Good alarm clock on a regular basis, TXT text, at once remove all the alarm clock, pay attention to the alarm clock music format with the storage path. Otherwise, it doesn't make any noise....
  Graph        C++     

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