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Advanced turbo decoder using VHDL

In information theory, turbo codes (originally in French turbocodes) are a class of high-performance forward error correction (FEC) codes developed in 1993, which were the first practical codes to closely approach the channel capacity, a theoretical maximum for the...
  vhdl      VHDL     

java MAP using JMAPViewer

This is a demo for JMAPViewer, import JMAPViewer will fix independency error. It shows how to use JMAPViewer to show open street MAP in your desktop application!...
  Java Development        Java     

Adder in VHDL

This program is an  adder for two floating numbers using VHDL language....
  vhdl      VHDL     

VHDL frequency meter

using the frequency meter VHDL write and modules divided into clear, basic principles for the detection of pulse signals in the life cycle of a gate frequency, use the four-segment digital tube display...
  vhdl      VHDL     

H264 motion estimation in VHDL

H264 estimation algorithms, VHDL description, detailed Readme document from github. FPGA and SOC can have a try....
  Algorithm      VHDL     

VHDL realization 8051 (full version)

VHDL realization 8051 (full version)...
  Algorithm      VHDL     

VHDL separator

VHDL PRograming its un aplicative tha it's performing at the memory ram  32 x 32 at rom 64 x 48...
  Windows      VHDL     

verilog and VHDL files

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port( clk: in std_logic; rst: in std_logic; q1: out std_logic); end tff1; architecture behavioral of tff1 is signal q: std_logic; begin process(clk,rst) begin...
  vhdl      VHDL     

Rs232 using VHDL

Disign RS232 controller using VHDL on Altera DE2. This is a serial module which is useful for embed systems....
  vhdl      VHDL     

Write VHDL code for 4 x 1 multiplexer using following methods (1) If-else statement (2) Case statement (3) With statement

Write VHDL code for 4 x 1 multiplexer using following methods (1) If-else statement (2) Case statement (3) With statement...
  vhdl      VHDL     

MAP of MAPCtrl

MAP library, using MAPInfo, interface is simple and powerful, and supports a variety of actions, supported language called c, or C++ call, has been tested, dynamic or static calls can be....
  Windows        C++     

3dMAP releases source code

3dMAP publishing source code. using 3dmax production model and import ArcMAP, Webcast...
  Windows        C#     

Blif2VHDL format conversion tool

A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

windows programming step by step

windows programming step by step book for detailed and comprehensive introduction to programming basics VC++, this book has 20 chapters, comprehensive and rich content, suitable for VC++ and related engineering technical personnel for beginners. For supporting this section of source code, easy...
  Windows        C++     

Serial port window call (API)

Serial dynamic libraries under the window, including open, sending and receiving, actions such as closing the serial port, and is developed by directly calling windowapi function....
  Windows        C++     

windows programming in English

windows programming, introduction, hope to those who need help...
  Windows        C++     

Lab windows code

Microsoft windows is a series of graphical interface operating systems developed, marketed, and sold by Microsoft. Microsoft introduced an operating environment named windows on November 20, 1985 as a graphical operating system shell for&n...
  Windows Kernel        C     

windows shut down applet

VB Development windows Auto shutdown function, call the API function, timing shutdown, shutdown, delay cancel the shutdown function....
  Windows        VB     

turbo decoder Release 0.3

turbo decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -turbo decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL mod...
  vhdl      VHDL     

VHDL sequential circuits

This circuit is a very simple VHDL sequential circuits through which circuit can clearly reactive VHDL timing principle as well as the most basic and simplest method of application,...
  Algorithm      VHDL     

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