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Full adder in Verilog

A simple Verilog code for full_adder. It is tested in both simulator and xilinx spartan3E fpga board. ...
  verilog      Verilog     

SPI flash model written by Verilog

M25Pxx ST company SPI flash memory Verilog simulation model, the model correctly describes the behavior of SPI flash memory, including reading, writing and erase operations, can be used to hang outside of the SOC with SPI interface, Verify that the SPI interface....
  verilog      Verilog     

Ledbanner in Verilog code using FPGA SPARTAN-3E

Ledbanner in Verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seVen segment display.  It will go from left to rigth or vise Versa. And will reset fuction when press reset botton....
  verilog      Verilog     

Veriolg HDL d flip-flop

D trigger program, suits the beginner to use and learn, Verilog HDL languages, using Xillinx's chips....
  verilog      Verilog     

8 bit adder Verilog

hey here is a ise format code for xilinx software Verilog 8 bit fixed point coding use this for example for coding with test bench...
  verilog      Verilog     

DESIGN OF 2X2 BIT VeDIC MULTIPLIER

IN THIS PROJECT ANCIENT VeDIC MATHEMATICS IS USED FOR THE MULTIPLICATION OPERATION.THE MULTIPLIER MAINLY USED IN  DIGITAL SIGNAL PROCESSORS,CRYPTOGRAPHIC ALGORITHM. URTHVA TRIYAGBHYAM  SUTRA IS USED FOR IMPLEMENTATION. UT IS SAID TO BE VeRTICAL AND CROSSWISE MULTIPLICATION....
  verilog      Verilog     

code Verilog cordic core

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details...
  verilog      Verilog     

Java using JNatiVe call DLL

Read ID information // Following is the main API functions Int CVR_InitComm (int Port) initiates the connection ; int CVR_Authenticate() 卡认证; int CVR_Read_Content(int actiVe) Card reader operation. int CVR_CloseComm() 关闭连接;...
  Java Development        Java     

Booth multiplier in Verilog

This file describes the code for booth multiplier in Verilog. the source code is simulated and Verified for better results...
  verilog      Verilog     

Verilog code for Vedic multiplier

This is the source code for 8x8 Vedic multiplier is designed by ancient Vedic mathematics. It contains 16 sutra in that urdhva tiryagbhyam suytra is used. For the addition operation full adder is used ....
  verilog      Verilog     

Verilog examples

Learn Verilog Common programming methods and examples. Welcome to download and trial. Thank you all for your support!...
  verilog      VHDL     

SOPC technology using Verilog create Hello program

SOPC technology FPGA Verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

DDS_Dual_ports Verilog implementation

DDS_Dual_ports Verilog implementation, you need to download experiment, according to their own needs to be modified in order to achieVe the purpose of its...
  verilog      Verilog     

Four lights switch of marquee (marquee program in Verilog_hdl languages)

This is a learning Verilog HDL good information, suitable for beginners, explained in detail, from the light into the deep, learning the language, it is a hardware description language for good stuff, good material!...
  verilog      Verilog     

Verilog serial port serial port receiVe module receiVer module

Verilog serial port serial port receiVe module receiVer module, contains the BPS modules, leVel detection module and the control module...
  verilog      Verilog     

Verilog simulation filters

Verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

Spring and Velocity for advanced applications

See contents Spring and Velocity for advanced applications Velicity utility classes defined using Spring managed bean...
  Java Development        Java     

Verilog for lsfr oVer bist

When desgin memories with larg portion, which include capacitance oVer bit-lines. The two bit-line are used perform a read and write operation, due to operation of discharging a capacitance in write operation. 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a...
  verilog      Verilog     

Verilog for booth multiplier

We are going to propose a new SRAM bitcell for the purpose of less power consumption, read stability,less area than the existing Schmitt trigger based SRAM and other existing designs through a new design which is combined of virtual grounding with Read error reduction logic.  ...
  verilog      Verilog     

IR receiVer Verilog modules

This module is suitable for all IR receiVer, please note that when using modified code, you receiVe is to identify user codes, code marked, thank you all for your support!...
  verilog      Verilog     

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