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Flash controller verilog code

2015-03-04 14:20    By:courageheart      View:363      Download:5

This is the verilog code of Samsung K9 series Flash controller, it is complied and verified on FPGA development board, the verification environment is quartusii and modelsim combined platform. You can find the datasheet of K9 flash on the internet. The size of the flash is 1024*32....

verilog Verilog

VGA color display the verilog code for Xilinx FPGA

2015-03-05 16:52    By:xinliu      View:417      Download:2

verilog implementation of FPGA VGA sesser stripes display code, test absolutely right, can successfully implement functionality....

verilog Verilog

AXI slave verilog code

2015-03-05 16:53    By:redleaf      View:187      Download:8

Wrote AXI slaver verilog code, hope to give you some inspiration...

verilog Verilog

1K SRAM seperate read and write ports, verilog code for ASIC design

2015-02-17 06:10    By:gucci1029      View:349      Download:2

1K SRAM, arranged as words of 32 bit, seperate read and write ports, verilog code for ASIC designusing even parity on count of 1's.also comes with testbench...

verilog VHDL

Parallel CRC verilog code generator

2015-03-01 08:49    By:KPROCKS      View:121      Download:2

A parllel CRC verilog generator has been written in C++ to generate a parallel CRC verilog code for a given user defined data width and CRC polynomial. This is from outputlogic.com . This a direct implementation algorithm used in the website....

verilog Verilog

Ledbanner in verilog code using FPGA SPARTAN-3E

2015-02-14 00:40    By:ren      View:134      Download:1

Ledbanner in verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.  It will go from left to rigth or vise versa. And will reset fuction when press reset botton....

verilog Verilog

4-bit counters verilog code

2015-02-18 03:47    By:caochishu      View:104      Download:0

One of the basics of verilog source code, binary counters for a 4. Both counts can be achieved to realize the frequency of the clock signal, so that is one very practical introduction to verilog code. On the basis of this code, you can make a variety of changes, to achieve different functionality....

verilog VHDL

verilog code FIFO

8 hours ago    By:sebastianleong      View:197      Download:1

FIFO is a First-In-First-Out memory queue with control logic that managesthe read and write operations, generates status flags, and provides optionalhandshake signals for interfacing with the user logic. It is often used tocontrol the flow of data between source and destination. FIFO can beclassifie...

verilog Verilog

verilog code for 8 bit array multiplier

2015-03-05 06:32    By:sonu      View:276      Download:2

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

verilog VHDL

verilog code for the GPS baseband processing

2015-03-03 03:00    By:jml8865      View:47      Download:0

GPS software receiver baseband processing verilog programs, by spread spectrum demodulation, intermediate frequency data synchronization process converts the raw navigation data...

verilog Verilog

verilog code for vedic multiplier

2015-03-02 01:22    By:duck      View:69      Download:1

This is the source code for 8x8 vedic multiplier is designed by ancient vedic mathematics. It contains 16 sutra in that urdhva tiryagbhyam suytra is used. For the addition operation full adder is used ....

verilog Verilog

verilog code for ECC processor using karatsuba multiplier

2015-02-11 22:23    By:heena      View:52      Download:0

We are working on a project based on side channel attacks caused in a ECC processor while performing multiplication....

verilog Verilog

UART verilog code

2015-02-11 08:39    By:my_lover      View:97      Download:0

Including uart baud rate selected transceiver and the underlying file, use any FPGA, proven verilog code....

Driver Development Verilog

verilog code for uart transmission

2015-03-03 19:39    By:shabbeerahamad      View:72      Download:2

the low power low cost data transmission teq done by UART chech it once it's writen in verilog language and also it's a protocol based where you are going to specify your own rules for better communication...

vhdl Verilog

this is the verilog code for discrete cosine transform in verilog

2015-02-09 02:28    By:mortin      View:58      Download:1

Abstract—Fault diagnosis plays an important role in physicalfailure analysis and yield learning process. With tens of billionsof transistors being integrated in one chip, multiple faults mayexist. With multiple faults, fault masking and reinforcing effectsmay appear. They may cause the conventiona...

Image Processing Verilog

verilog code for SDRAM

7 hours ago    By:hanhaizhizi      View:94      Download:1

SDRAM driver, written in the verilog language, verilog reference those things is coming from, and is divided into three modules, initialize the module, the function module and the control module, the module which has a total of three modules together. 4bank row width column widths are 12-8-bit SDRAM...

Driver Development Verilog

verilog Jpeg Encoder

2015-03-03 09:50    By:thuanbk2010      View:724      Download:10

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bit stream necessary to build a jpeg image. The core was written in generic, regular verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores,...

verilog Verilog

Full adder in verilog

2015-03-03 02:18    By:arishsu      View:198      Download:0

A simple verilog code for full_adder. It is tested in both simulator and xilinx spartan3E fpga board. ...

verilog Verilog
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