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jpegdecoder(VHDL)

The JPEG standard (ISO/ IEC 10918-1 ITU-T Recommendation T.81) defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only...
  video      VHDL     

barrel shifter

A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an implementation the output of one mux is conne...
  vhdl      VHDL     

Course design of EDA-24 hour digital

Course design of EDA-24 hour digital                     ...
  vhdl      VHDL     

8,051 communication based on VHDL

8,051 features based on VHDL simulation, serial communications, down under in need can have a look at, there is quite a lot of things, carefully and slowly card go under....
  Embeded      VHDL     

Advanced VHDL six-bit Adders

Addition of hardware description language VHDL design of electronic design automation. Design-thinking ahead carry ideas, designed to achieve six-bit binary number summed together....
  vhdl      VHDL     

advanced encryption standard

this is advanced encryption standard code written in vhdl. you can simulate and check the result using xilinx ise or modelsim simulator tools..........
  Other      VHDL     

Vdhl realization of shift function

Vdhl realization of shift function                        ...
  vhdl      VHDL     

0-9999 counter on 7Segment for DE1 boards

this is a simple counter for DE1 boards.it count 0-9999 on seven segments. it`s in VHDL language...
  vhdl      VHDL     

vhdl source code

this project is a simulator for a CPU and RAM in VHDL language . The program is written in binary code in the RAM will be executed by the CPU components . The code is tested on FPGA technology ....
  Embeded      VHDL     

Design of 32-bit pipelined MIPS CPU

The design of CPU lines divided into 4 levels: fetch (IF), the instruction decoding (DOF), the Executive (EX), write back (WB). Solve order of data between adjacent instructions when related issues. Skip/branching instructions require two clock of stall. CPU hardware modules including: program...
  vhdl      VHDL     

Encoder count is implemented by VHDL

VHDL test the encoder output for main and count, for example, is the encoder resolution is 1000, issued around 1000 pulses, the program mainly records the number of pulses, pulse representing the number of a certain point of view, so by pulse number can reflect objects turning angle, position detect...
  vhdl      VHDL     

vga800x600

Timing 800x600 VGA mode clearly shows a site has passed authentication can use are based on Xilinx Spartant3e Development Board. Verilog language implementation....
  fpga      VHDL     

基于fpga 数字存储示波器

 library ieee; use IEEE.std_logic_1164.all; entity ad5510 is  port( rst,clk: in std_logic;    d: in std_logic_vector(7 downto 0);    adck,DCLK:out std_logic;    Q: out std_logic_vector(7 downto 0)); end ad5510; architecture adctrl...
  Arm      VHDL     

DCT IDCT VHDL FIX

It is the code for compressing image using DCT&IDCT using VHDL in FPGA. The code I write in docx to make it small size. The source comes from xilinx but it didn't work so I fix some error :D Enjoy....
  Image Processing      VHDL     

Turbo Decoder

Turbo Encoder, Decoder Matlab Code                  ...
  Embeded      VHDL     

VGA display Chinese characters available on the spartan3e

Programs written in VHDL language, via the VGA port to display Chinese characters, on the spartan3e entry-level development board test is successful, good code source, please download...
  vhdl      VHDL     

Verilog HDL Digital clocks digital tube display

Verilog HDL digital clock digital display: EP2C5Q208C8N for chip Development Board debug through. The code can achieve key addition and subtraction operations with hours, minutes, and seconds....
  verilog      VHDL     

RLS adaptive algorithm to write your own, you can achieve a better filter

RLS adaptive algorithm to write your own can achieve a better filter. Based on RLS adaptive filters, Fourier transform, a MATLAB simulation have been uploaded...
  Matlab      VHDL     

16 bit radix-2 implimentation of cordic algorithm

This code iss used for computation of sine and cosine  using CORDIC algorithm .IT takes 16 bit nos ,CORDIC is hardware efficient algorithm,which computes sine and cosine even when hardware multipliers are not available...
  verilog      VHDL     

VHDL realization of divider

This code successfully implement a divider, ModelSim Simulation successfully, or Xilinx Spartan-3 connecting with hardware implementation. This code also implements the input divisor, dividend output quotient and remainder with realistic features LED lights. Content. the UCF file and the LEDDISPLA f...
  vhdl      VHDL