SIMULINK MODEL FOR FINDING BIT ERROR RATE FOR qam OFDM
OFDM WITH qam MODULATION...
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using FPGA verilog HDL simulation class I2C communication
using FPGA verilog HDL simulation class I2C communication...
verilog Verilog 
digital to analog convertor using vhdl ams
Its a project baded on implementing digital to analog convertor using VHDL-AMS using behavourial as well as structural abstractions.... vhdl VHDL speech compression using LPC
this file is used to do the compression using the Linear predictive coding...
thread Matlab lexicalAnalyzer source code ..using C++
lexicalAnalyzer source code ..using C++...
compiler program 
C++ HI,i am an ec student....i wanted code for airport simulation problem in datastructures using C
HI, friends im an ec student ......i recently attended a workshop on data structures using C in colg they have given me a mini project in that i hav chosen this topic of airport simulation problem so pls help me in getting the code...
book 
C 
target tracking using kalman
Target tracking using kalman filter to estimate the movement of target.... Matlab Matlab 
Serial communication using QtSerialPort
there are many bugs like non-precise reading... communication C++ aumented reality using neural network
in this we are selecting marker it may either be spherical or pyramid shape and color we have to choose ... Matlab Matlab face recognition using PCA
Principal component analysis is a technique used in statistical pattern recognition for data reduction and feature extraction. As the pattern mostly contain redundant in...
Algorithm Matlab Iterative Decoding of Concatenated Convolutional Codes
Iterative Decoding of Concatenated Convolutional Codes... Matlab C using verilog language organ procedures. GW48 teaching experiment with simulatio...
using verilog language organ procedures. GW48 teaching experiment with simulation boxes... VHDL-FPGA-Verilog VHDL uart serial port, using verilog prepared. For your reference...
uart serial port, using verilog prepared. For your reference... VHDL-FPGA-Verilog 
Others using verilog write a good cpu core...
using verilog write a good cpu core... VHDL-FPGA-Verilog Others Source code for asyn_fifo using verilog language....
Source code for asyn_fifo using verilog language.... VHDL-FPGA-Verilog VHDL
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