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16 bit risc processor for computer hardware

16 bit risc processor for computer hardware ...
  Algorithm      VHDL     

WarmOS 16-bit real mode operating systems

WarmOS is a 16-bit real mode operating system written with compilation, it includes some of the basic functions of the operating system should have, support implementation of the COM file format, providing some system API for programmers to write programs, and from the kernel to support Chinese disp...
  OS Develop        ASM     

Using FPGA verilog HDL simulation class I2C communication

Using FPGA verilog HDL simulation class I2C communication...
  verilog      Verilog     

1602+DS18B20+PWM control

1602+DS18B20+PWM control...
  单片机        C     

LCD 1602 codes HD44780 compatible

LCD 1602 codes HD44780 compatible DBASE III compiler HITEC PICC 9.83 6 online mode R/W foot grounded...
  SCM        C     

LCD 1604 codes HD44780 compatible

LCD 1604 codes HD44780 compatible DBASE III compiler HITEC PICC 9.83 6 online mode R/W foot grounded...
  SCM        C     

VTK arbitrary two-dimensional image trimming

VTK arbitrary two-dimensional image trimming program, very nice, by visual studio MFC...
  Graph        Visual C++     

SIMULINK MODEL FOR FINDING bit ERROR RATE FOR QAM OFDM

OFDM WITH QAM MODULATION...
  Matlab        Matlab     

i got this 16

i got this 16-bit huffman codec from abroad website. we usually use 8-bit huffman codec. this source code is especially useful for medical image process....
  Compress-Decompress algrithms        Visual C++     

Written in verilog IP core, 512K 16

Written in verilog IP core, 512K 16-bit SRAM...
  VHDL-FPGA-Verilog        Others     

design cpu 16 bits by verilog HDL....

design cpu 16 bits by verilog HDL....
  VHDL-FPGA-Verilog      VHDL     

this is the ALtera devoted second

this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation...
  VHDL-FPGA-Verilog        Others     

See 16

See 16-bit color, (RBG: 5:6:5) color format can be converted into 24-bit color 16....
  GDI-Bitmap        Visual C++     

an embedded risc CPU design verilog source code can be integrated. Detailed desi...

an embedded risc CPU design verilog source code can be integrated. Detailed design containing the text block....
  ARM-PowerPC-ColdFire-MIPS        Others     

verilog HDL

verilog HDL-based 16-bit CLA is divided into three functional sub-modules...
  VHDL-FPGA-Verilog      VHDL     

verilogHDL language based on the 16

verilogHDL language based on the 16-bit multiplier of the booth algorithm and test code...
  VHDL-FPGA-Verilog      VHDL     

uart16550 ip core UART VHDL source code...

uart16550 ip core UART VHDL source code...
  VHDL-FPGA-Verilog      VHDL     

The design of a programmable interval timer, 8253 to complete the function, real...

The design of a programmable interval timer, 8253 to complete the function, realize the following requirements: 1, contains three independent 16-bit counter, capable of three independent 16-bit count. 2, each with six counter mode. 3, can be binary/decimal subtraction count. 4, can be used for the t...
  VHDL-FPGA-Verilog        Others     

This leon3 design is tailored to the Altera NiosII Startix2 Development board,...

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled...
  VHDL-FPGA-Verilog        Others     

This is an 16 bit adder using vhdl...

This is an 16 bit adder using vhdl...
  VHDL-FPGA-Verilog      VHDL