This is a project about VLSI design.Topic
is design for motion compensated prediction block in compressed
video.Project consisted code RTL,code Testbench.
use software of synopsys for example: Design Compiler (Synthesis),IC Compiler (Layout)...... verilogVerilog
This is a project about VLSI design.Topic is design for CORDIC (for COordinate Rotation DIgital Computer),also known as the digit-by-digit method and Volder's algorithm.Project consisted code RTL,code Testbench.
Project use software... verilogVerilog
This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bitstream necessary to build a jpeg image. The core was written in generic, regular verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores,... verilogVerilog
M25Pxx ST company SPI flash memory verilog simulation model, the model correctly describes the behavior of SPI flash memory, including reading, writing and erase operations, can be used to hang outside of the SOC with SPI interface, verify that the SPI interface.... verilogVerilog
A parllel CRC verilog generator has been written in C++ to generate a parallel CRC verilog code for a given user defined data width and CRC polynomial. This is from outputlogic.com . This a direct implementation algorithm used in the website.... verilogVerilog
Ledbanner in verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.
It will go from left to rigth or vise versa. And will reset fuction when press reset botton.... verilogVerilog
This is a learning verilog HDL good information, suitable for beginners, explained in detail, from the light into the deep, learning the language, it is a hardware description language for good stuff, good material!... verilogVerilog
One of the basics of verilog source code, binary counters for a 4. Both counts can be achieved to realize the frequency of the clock signal, so that is one very practical introduction to verilog code. On the basis of this code, you can make a variety of changes, to achieve different functionality.... verilogVHDL
We are going to propose a new SRAM bitcell for the
purpose of less power consumption, read stability,less area than the existing
Schmitt trigger based SRAM and other existing designs through a new design
which is combined of virtual grounding with Read error reduction logic.
Using verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,... verilogVerilog