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Blif2vhdl format conversion tool

A BLIF to vhdl converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....
  vhdl        C     

vhdl for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
  vhdl      VHDL     

vhdl4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you start answering as a violation vie, violation vie warns players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...
  vhdl      VHDL     

I2CvhdlASDASDADASD

Content is too short. Attention please: Codes without good description will be deleted and you won't get any points. Please describe it better to get more points....
  vhdl      VHDL     

Simpleteam

SimpleAPI can run on Windows, Linux, FreeBSD, Solaris, AIX, and other support JVM OS; operating environment require JDK 1.4.x or later (including JDK 1.4.x). You can click here to download the SimpleAPI Development Kit SimpleAPI.jar; used to tie in with the development gateway Simulator parts Gatewa...
  Linux programming        Java     

vhdl realization 8051 (full version)

vhdl realization 8051 (full version)...
  Algorithm      VHDL     

vhdl separator

vhdl PRograming its un aplicative tha it's performing at the memory ram  32 x 32 at rom 64 x 48...
  Windows      VHDL     

car racing_vhdl

This code is a car racing program in vhdl which is developed using xilinx spatan 3e board. This code is developed on the EDK platform, It has following modules 1. Buttons_4bit 2. Clock Generator 3. Debug module EDK is a emebedded development kit plaform from xili...
  Embeded      VHDL     

H264 motion estimation in vhdl

H264 estimation algorithms, vhdl description, detailed Readme document from github. FPGA and SOC can have a try....
  Algorithm      VHDL     

vhdl obtaining quadrature

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; Library UNISIM; use UNISIM.vcomponents.all; --------------------------------------------------------------------...
  signal Processing      VHDL     

vhdl code for Adder / Subtractor

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY adder IS PORT(Cin        : IN STD_LOGIC; Carry        : IN STD_LOGIC;  X,Y        : IN STD_LOGIC_VE...
  Matlab      VHDL     

vhdl sequential circuits

This circuit is a very Simple vhdl sequential circuits through which circuit can clearly reactive vhdl timing principle as well as the most basic and Simplest method of application,...
  Algorithm      VHDL     

vhdl and verilog implementation of dds and fft

The core component of a DDS waveform generator is the accumulator. The accumulator is a running counter which stores the current phase value of the generated waveform. The rate at which the accumulator is updated and the accumulator increment value determine the frequency of the generated waveform....
  Windows      VHDL     

Simple_write.c

#include <unistd.h> #include <stdlib.h> int main() { if ((write(1, “Here is some data\n”, 18)) != 18) write(2, “A write error has occurred on file descriptor 1\n”,46); exit(0); }...
  Linux programming        C     

Simple calculator.

calculator. C language completely. Writing a with functions of addition, subtraction, multiplication, and division arithmetic Calculator program. To make it easier to achieve, in our calculators using reverse Poland expression instead of ordinary infix notation. Inverse Poland notation,...
  CSharp        C     

Waveform generator and sine waveforms generator based on vhdl language

Waveform generator and sine waveforms generator based on vhdl language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to vhdl is also helpful to-This i...
  vhdl      VHDL     

Learn vhdl displays a six-digit

During the eight-digit seven-segment digital display control display on 8-bit 学号 , To display the 的 学号 You can ride Sequence changes, device validation error-free and running well....
  vhdl      VHDL     

Realization virtual electric piano based on vhdl

This program design using vhdl language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...
  vhdl      VHDL     

Wavelet transform and vhdl

Wavelet transform in JPEG2000 part of the vhdl source code. JPEG2000 The core algorithm is based on Discrete Wavelet transform. Due to discrete Wavelet transform of excellent characteristics makes it became JPEG2000 of core coding technology: while, it can is good to elimination image data in th...
  vhdl      VHDL     

vhdl code for latch_ff_comb for d_comb ckt in vhdl

library ieee; use ieee.std_logic_1164.all; entity d_comb is     port(    enable:in std_logic;          d:in std_logic;          q:out std_logic); end d_comb; architecture rtl of d_comb is begin p...
  vhdl      VHDL     

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