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2812 board cpld learning source...

2812 board cpld learning source...
  ARM-PowerPC-ColdFire-MIPS      VHDL     

cpld bus Verilog HDL code, the PLD

cpld bus Verilog HDL code, the PLD-10 Quartus4 platform to run through....
  VHDL-FPGA-Verilog        C++     

TMS320F2812 with cpld extended IO programs that I bought a program on the circui...

TMS320F2812 with cpld extended IO programs that I bought a program on the circuit board QQ2812, after I debug, fully available....
  DSP program        C++     

STC51 MCU 128K sram experimental C

STC51 MCU 128K sram experimental C-language program to read and write, serial debugging assistant display....
  SCM        C++     

Abstract: This paper introduces the cpld chip to the traffic lights at the cross...

Abstract: This paper introduces the cpld chip to the traffic lights at the crossroads of design, traffic lights with cpld as the master controller chip, the use of VHDL language control procedures, the use of cpld re-programming and dynamic system reconfiguration in the features greatly enhance the...
  VHDL-FPGA-Verilog      VHDL     

ZBT sram controller reference design for Xilinx (ZBT sram, a high

ZBT sram controller reference design for Xilinx (ZBT sram, a high-speed synchronous sram)...
  VHDL-FPGA-Verilog        Others     

STM32F103VBT6 realize sram...

STM32F103VBT6 realize sram...
  SCM        C++     

An sram of the source program, it is the sram 256kbx16bit...

An sram of the source program, it is the sram 256kbx16bit...
  VHDL-FPGA-Verilog      VHDL     

This is a sram interface driver, to drive the sram 256kbx16bit...

This is a sram interface driver, to drive the sram 256kbx16bit...
  Driver Develop        Visual C++     

Verilog FPGA code languages. Pc machine functions through a number of epp consta...

Verilog FPGA code languages. Pc machine functions through a number of epp constantly write to the sram, and then pc send interrupt signals to interrupt the process of writing to read the data in the sram. rar package includes epp agreement, modules and test documents (test)....
  Other Embeded program        Others     

cpld initialization procedure for the DSP5416 and the timing control SAA7111A in...

cpld initialization procedure for the DSP5416 and the timing control SAA7111A initialization....
  Embeded-SCM Develop      VHDL     

This paper describes a combined use of SCM and cpld stepper motor control progra...

This paper describes a combined use of SCM and cpld stepper motor control program. First of all, to clarify the working principle of stepper motor and control method, and then put forward a system of hardware and software design framework for a detailed discussion of the MCU and cpld logic interface...
  SCM        PDF     

ATEREAL EPM1270T144C5N cpld

ATEREAL EPM1270T144C5N cpld-based pressure sensor data acquisition source Quartus II development software...
  VHDL-FPGA-Verilog      VHDL     

Written in Verilog IP core, 512K 16

Written in Verilog IP core, 512K 16-bit sram...
  VHDL-FPGA-Verilog        Others     

based cpld FSK signal generator design. PDF...

based cpld FSK signal generator design. PDF...
  Embeded-SCM Develop        Others     

cpld

cpld-based signal generator multifunctional design. PDF...
  Embeded-SCM Develop        Others     

sram

sram-based reconfigurable circuit...
  Document        Others     

Mainly on the timing and the Principle sram_512k61LV25616...

Mainly on the timing and the Principle sram_512k61LV25616...
  Embeded-SCM Develop        Others     

FPGA

FPGA-controlled sram interface design, regardless of...
  VHDL-FPGA-Verilog      VHDL     

sram read and write small programs using Verilog prepared, please enlighten you...

sram read and write small programs using Verilog prepared, please enlighten you master...
  VHDL-FPGA-Verilog        Others