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Using FPGA verilog HDL simulation class I2C communication

Using FPGA verilog HDL simulation class I2C communication...
  verilog      Verilog     

Countdown clock

VHDL countdown clock, Countdown to A,B at the same time, the LCD display...
  sock      VHDL     

Digital clock of MSP430

Collector's Edition of the c code for MSP430 digital clock...
  CSharp        C     

Qt clock interface

Simple clock written with Qt interface by implementing a paintEvent function to draw...
  GUI        C++     

verilog clock divider ~ 50hmz, using baud rate 9600bps ~...

verilog clock divider ~ 50hmz, using baud rate 9600bps ~...
  VHDL-FPGA-Verilog        Others     

In this study, the use of 8253 to do the timer, using timer pulse output control...

In this study, the use of 8253 to do the timer, using timer pulse output control 8259 generates an interrupt in 8259 interrupt handler, for hours, minutes and seconds count, waiting for interruption through ring using LED display time. 8253 with the timer/counter 1,8253 chip select access CS4, a...
  Other Embeded program        ASM     

verilog clock control procedures to prepare, in the Xilinx chip development. Ant...

verilog clock control procedures to prepare, in the Xilinx chip development. Anti-shake, such as with the case considered...
  Communication        C++     

verilog language using an electronic bell procedures. GW48 is teaching me the ex...

verilog language using an electronic bell procedures. GW48 is teaching me the experimental simulation...
  SCM      VHDL     

DIVIDE...

DIVIDE...
  VHDL-FPGA-Verilog      VHDL     

With verilog HDL realize arbitrary frequency divider source code, is a generic p...

With verilog HDL realize arbitrary frequency divider source code, is a generic procedure...
  VHDL-FPGA-Verilog      VHDL     

divider verilog code for multiple sub

divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation...
  VHDL-FPGA-Verilog      VHDL     

VHDL description of the clock divider circuit, uses widely ......

VHDL description of the clock divider circuit, uses widely ......
  VHDL-FPGA-Verilog        Others     

The document may download to FPGA chip to complete the clock divider,serial

The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation...
  VHDL-FPGA-Verilog      VHDL     

an divider using vhdl...

an divider using vhdl...
  VHDL-FPGA-Verilog      VHDL     

FPGA/CPLD applications, UART verilog HDL source...

FPGA/CPLD applications, UART verilog HDL source...
  Communication        Others     

Times (times) divider Please note: This case is described in various sources to...

Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd...
  VHDL-FPGA-Verilog      VHDL     

Design and verification verilog_ examples Hdl classic books, strongly recommend....

Design and verification verilog_ examples Hdl classic books, strongly recommend...
  VHDL-FPGA-Verilog      VHDL     

an electronic experiments of verilog source code. Suitable for beginners learnin...

an electronic experiments of verilog source code. Suitable for beginners learning verilog reference...
  VHDL-FPGA-Verilog        C++     

based on VHDL description of a divider, according to port value, as a quarter of...

based on VHDL description of a divider, according to port value, as a quarter of frequency, Frequency divider interval such use....
  VHDL-FPGA-Verilog        Others     

verilog program for real time clock.. select the .v file to view the code....

verilog program for real time clock.. select the .v file to view the code....
  VHDL-FPGA-Verilog      VHDL