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VGA color display the verilog code for Xilinx FPGA

verilog implementation of FPGA VGA sesser stripes display code, test absolutely right, can successfully implement functionality....
  verilog      Verilog     

AXI slave verilog code

Wrote AXI slaver verilog code, hope to give you some inspiration...
  verilog      Verilog     

Parallel CRC verilog code generator

A parllel CRC verilog generator has been written in C++ to generate a parallel CRC verilog code for a given user defined data width and CRC polynomial. This is from outputlogic.com . This a direct implementation algorithm used in the website....
  verilog      Verilog     

Ledbanner in verilog code using FPGA SPARTAN-3E

Ledbanner in verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.  It will go from left to rigth or vise versa. And will reset fuction when press reset botton....
  verilog      Verilog     

4-bit counters verilog code

One of the basics of verilog source code, binary counters for a 4. Both counts can be achieved to realize the frequency of the clock signal, so that is one very practical introduction to verilog code. On the basis of this code, you can make a variety of changes, to achieve different functionality....
  verilog      VHDL     

verilog code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....
  verilog      VHDL     

verilog code for the GPS baseband processing

GPS software receiver baseband processing verilog programs, by spread spectrum demodulation, intermediate frequency data synchronization process converts the raw navigation data...
  verilog      Verilog     

verilog code for vedic multiplier

This is the source code for 8x8 vedic multiplier is designed by ancient vedic mathematics. It contains 16 sutra in that urdhva tiryagbhyam suytra is used. For the addition operation full adder is used ....
  verilog      Verilog     

verilog code for ECC processor using karatsuba multiplier

We are working on a project based on side channel attacks caused in a ECC processor while performing multiplication....
  verilog      Verilog     

UART verilog code

Including uart baud rate selected transceiver and the underlying file, use any FPGA, proven verilog code....
  Driver Development      Verilog     

verilog code for SDRAM

SDRAM driver, written in the verilog language, verilog reference those things is coming from, and is divided into three modules, initialize the module, the function module and the control module, the module which has a total of three modules together. 4bank row width column widths are 12-8-bit SDRAM...
  Driver Development      Verilog     

verilog jpeg

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bitstream necessary to build a jpeg image. The core was written in generic, regular verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores,...
  verilog      Verilog     

Full adder in verilog

A simple verilog code for full_adder. It is tested in both simulator and xilinx spartan3E fpga board. ...
  verilog      Verilog     

verilog simulation filters

verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...
  verilog      Verilog     

8 bit adder verilog

hey here is a ise format code for xilinx software verilog 8 bit fixed point coding use this for example for coding with test bench...
  verilog      Verilog     

SPI flash model written by verilog

M25Pxx ST company SPI flash memory verilog simulation model, the model correctly describes the behavior of SPI flash memory, including reading, writing and erase operations, can be used to hang outside of the SOC with SPI interface, verify that the SPI interface....
  verilog      Verilog     

verilog examples

Learn verilog Common programming methods and examples. Welcome to download and trial. Thank you all for your support!...
  verilog      VHDL     

SOPC technology using verilog create Hello program

SOPC technology FPGA verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

Median filter

Development of FPGA-based 3*3 template Median filter, filter disadvantage is that the image is blurred, because it is treated in the same way to all points, the noisy, Assessed at the same time, to landscape border crossing points were also assessed. In order to improve its effectiveness, w...
  verilog      Verilog     

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