Search vhdl floating point multiplier, 300 result(s) found

vhdl for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...

Blif2vhdl format conversion tool

A BLIF to vhdl converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included)....

2013-10-31 00:03

vhdl and verilog implementation of floating point adder ieee754

IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier – all 0s is smallest exponent all 1s is largest – bias of 127 for single precision and 1023 for double precision – summary: (–1)sign × (1+significand)...

2013-10-31 00:12
by bala


Content is too short. Attention please: Codes without good description will be deleted and you won't get any points. Please describe it better to get more points....

vhdl4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you start answering as a violation vie, violation vie warns players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...

2013-12-12 05:03

FPU floating point unit verilog vhdl

FPU (floating point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...

vhdl Design of 16 Radix 4 point FFT

Design and functional implementation of a 16-point pipelined FFT architecture is presented.  The architecture is based on the radix-4 algorithm.  By exploiting the regularity of the algorithm, butterfly operation and multiplier modules were designed.  The architect...

2014-06-12 02:36

vhdl frequency meter

Using the frequency meter vhdl write and modules divided into clear, basic principles for the detection of pulse signals in the life cycle of a gate frequency, use the four-segment digital tube display...

2014-08-29 05:22

vhdl 100 examples

Share online for some 100 examples suitable for FPGA learning for beginners. Inside there are some classic tricks....

2014-10-12 09:37
by ydk

vhdl realization of 3*3 matrix multiplication

Matrix multiplication vhdl implementation, dimension fixed, very instructive.Focus on understanding the interface, timing settings, delay control. Because the structure is relatively clear, not added stimulus file, you can write your own....

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