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Freetype-2.4.0.tAr

Font engine font engine font engine font engine font engine font engine font engine font engine font engine font engine...
  字体引擎        C     

Boeing 747 flight simulation model for six degree of Freedom space-Simulink procedures. rAr

The Boeing 747 space simulation model-Simulink procedure. rAr Boeing 747 space simulation model-Simulink procedure. rAr Boeing 747 space simulation model-Simulink procedure. rAr...
  Algorithm        Matlab     

OFDM transciever implementation By using FPGA written invhdl

This extension is written to add cognitive radio (CR) capabilities to the Network Simulator-3. It will cover the installation process, the documentation of such an extension and provide examples to get you stArted. We call this extension module CRE-NS3. This extension provides the basic block...
  software      VHDL     

Adder in vhdl

This program is an  adder for two floating numbers using vhdl language....
  vhdl      VHDL     

vhdl frequency meter

Using the frequency meter vhdl write and modules divided into cleAr, basic principles for the detection of pulse signals in the life cycle of a gate frequency, use the four-segment digital tube display...
  vhdl      VHDL     

mifAre mfrc531

The MIFArE Classic family is the pioneer and front runner in contactless smArt cArd ICs operating in the 13.56 MHZ frequency range with read/write capability and ISO 14443 compliance. SmArt cArds based on MIFArE Classic ICs Are widely used and a commonly known solution in vArious applications suc...
  Arm        C++     

UArt LiblAry for avr

This librAry can be used to transmit and receive data through the built in UArT.   *  *  An interrupt is generated when the UArT has finished transmitting or  *  receiving a Byte. The interrupt handling routines use circulAr buffers  *  for buffering recei...
  Arm        C     

ArM embedded

STM32Arm slave HID the program, the host recognizes the device, slave control PC's mouse to control mouse movement....
  Arm        C     

LPC1788 ,UArT

The example is USB to UArT (UArT0) for LPC1788. This example describes how to use UArT interface on LPC177x_8x....
  Arm        C     

Blif2vhdl format conversion tool

A BLIF to vhdl converter (51K compressed tAr, with SunOS, SolAris, and Linux binAries. Source code (C++) included)....
  vhdl        C     

Rs232 using vhdl

Disign RS232 controller using vhdl on Altera DE2. This is a serial module which is useful for embed systems....
  vhdl      VHDL     

Write vhdl code for 4 x 1 multiplexer using following methods (1) If-else statement (2) Case statement (3) With statement

Write vhdl code for 4 x 1 multiplexer using following methods (1) If-else statement (2) Case statement (3) With statement...
  vhdl      VHDL     

Fast Vedic Mathematic Multiplication using vhdl

This document contains the detail contents for the vedic multiplier in vhdl. It contents the detial explaination of the vedic multiplier process....
  vhdl      VHDL     

Waveform generator and sine waveforms generator based on vhdl language

Waveform generator and sine waveforms generator based on vhdl language, a total of two files, communication development platform. This is a typical black wave generator program and an ArbitrAry waveform generator program, members can refer to the study, introduction to vhdl is also helpful to-This i...
  vhdl      VHDL     

vhdl 100 examples

ShAre online for some 100 examples suitable for FPGA leArning for beginners. Inside there Are some classic tricks....
  vhdl      VHDL     

verilog and vhdl files

librAry ieee; use ieee.std_logic_1164.all; use ieee.std_logic_Arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port( clk: in std_logic; rst: in std_logic; q1: out std_logic); end tff1; Architecture behavioral of tff1 is signal q: std_logic; begin process(clk,rst) begin...
  vhdl      VHDL     

vhdl simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several pArts through QuArtusII 9 compiler testing is feasible. Code original containing syste...
  vhdl      VHDL     

vhdl4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you stArt answering as a violation vie, violation vie wArns players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...
  vhdl      VHDL     

ArM based lcd program By Er.Shivam Gupta

This program i created for ArM processor i want to control my lcd with ArM processor i have use ArM 32bit lpc2124 processor i connect the lcd on port 0 on 8-bit mode and read the analog value from the vAriable resistor and adc convert it into digital and show adc value on lcd in terms of voltage....
  Arm        C     

DalaunAry triangulAr meshes

Provider and source code from the uploaded file, you can open the solution to run, and browse the program, which also has form on how to run the program. If you have any questions you can look at the documentation provided, and hope you can gain something, thank you! If you need to dalaunAry of tria...
  CSharp        C#     

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