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Similarity xsimilarity-master

Chinese words, and group block, and sentence and text chapter, all level of similar degrees calculation is Chinese information processing field of a items based and and core of work, it directly decided with related field of research development condition, such as, in knowledge works, and based on i...
  相似度计算        Java     

ULIP vxsim Network Simulation and Implementation...

ULIP vxsim Network Simulation and Implementation...
  Embeded-SCM Develop        Others     

contains good LWIP transplantation, and CS8900 chip Network Driver...

contains good LWIP transplantation, and CS8900 chip Network Driver...
  Other Embeded program        C++     

More than a few basic electrical test engineering, and analysis of the code has...

More than a few basic electrical test engineering, and analysis of the code has is a good material for beginners...
  WinSock-NDIS      VHDL     

ajax example,. net under a very simple application, gird...

ajax example,. net under a very simple application, gird...
  source in ebook        JavaScript     

Prepared using Verilog table tennis game, with band ps2, VGA driver, download to...

Prepared using Verilog table tennis game, with band ps2, VGA driver, download to spantan3 development board to use (original)...
  VHDL-FPGA-Verilog        Others     

Computer Architecture, on the DLXS the simulation program. Under the vc6.0 compi...

Computer Architecture, on the DLXS the simulation program. Under the vc6.0 compile....
  ARM-PowerPC-ColdFire-MIPS        Visual C++     

Using FPGA digital phase

Using FPGA digital phase-locked loop, development environment for ISE...
  VHDL-FPGA-Verilog      VHDL     

eda text ise vhdl...

eda text ise vhdl...
  Other systems      VHDL     

Source codes for verilog fifo for spartan 3...

Source codes for verilog fifo for spartan 3...
  software engineering        PDF     

Alpha

Alpha-data acquisition card, is Gigabit Ethernet, LVDS, PCI/PCI-X of the VHDL program...
  Other systems      VHDL     

Introduction This is a soft 32

Introduction This is a soft 32-bit RISC processor core design and verification...
  Fax program      VHDL     

VerilogHDL write with a RISC processor...

VerilogHDL write with a RISC processor...
  ARM-PowerPC-ColdFire-MIPS        Visual C++     

c of the source numerical algorithm is a very classic books, can be used in many...

c of the source numerical algorithm is a very classic books, can be used in many ways...
  Mathimatics-Numerical algorithms        C++     

verilog source code for uart design...

verilog source code for uart design...
  software engineering        PDF     

Using FPGA to achieve CRC algorithm, only one pulse will be able to realize, tha...

Using FPGA to achieve CRC algorithm, only one pulse will be able to realize, than the traditional algorithm greatly saving time shift...
  VHDL-FPGA-Verilog      VHDL     

Manual for DSP sp3 for students who do coding...

Manual for DSP sp3 for students who do coding...
  DSP program        PDF     

fifo using handshake protocol

in this project we use VHDL to implement the fifo using handshake protocol to the fpga. it a two clocks for reading and writing respectively. this project is our final requirement in finals. thank you for considering this....
  verilog      VHDL     

股市模拟SWARM JAVA程序

  1. 交易者类 import swarm.objectbase.SwarmObjectImpl; import swarm.Globals; import swarm.defobj.Zone; import swarm.gui.Raster; import swarm.space.Grid2dImpl;   /**  * <p>Title: Agent.java</p>  ...
  Java Development        Java     

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