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verilog uart 115200

Using serial port UART transmission module written in verilog, sending rate to 115200, input clock for 50m for many years validation without errors...
  verilog      Verilog     

verilog design water lights

Under water lights in the verilog language module Design. Are the clock pulses + counters +LED control...
  verilog      Verilog     

verilog temperature control commands

verilog temperature control command realizes the temperature acquisition and operation, as well as other control  commands very well...
  verilog      Verilog     

VEDIC MULTIPLIER USING PROPOSED 4 bit adder-(URDHVA TIRYAKBHYAM)

VEDIC MULTIPLIER TAKES LESS TIME TO PERFORM THE MULTIPLICATION OPERATON USING THE URDHVA TIRYAKBHYAM ALGORITHM FROM THE VEDAS.THIS SOURCE CODE IS A 4 X 4 VEDIC MULTIPLIER USING PROPOSED 4 bit adder...
  verilog      Verilog     

verilog spwm

Second-class Prize in electronic design contests, implemented in the FPGA, two-way natural sampling SPWM...
  verilog      Verilog     

verilog LED spartan 6

This code is the verilog code, and spartan 6 model specification code. Welcome to download and try. Thank you for your support....
  verilog      Verilog     

Using FPGA verilog HDL simulation class I2C communication

Using FPGA verilog HDL simulation class I2C communication...
  verilog      Verilog     

verilog for lsfr over bist

When desgin memories with larg portion, which include capacitance over bit-lines. The two bit-line are used perform a read and write operation, due to operation of discharging a capacitance in write operation. 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a...
  verilog      Verilog     

verilog Arbiter

A four level, round-robin arbiter. This was orginally coded by WD Peterson in VHDL...
  verilog      Verilog     

code verilog cordic core

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details...
  verilog      Verilog     

DDR2 controller, verilog source code

Using verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...
  verilog      Verilog     

Introduction to verilog

This article introduces the basics of verilog HDL language, to enable the beginner to quickly grasp the HDL Design methods, preliminary reports and to master the basics of verilog HDL language, to be able to read simple design code and Enough to make some simple verilog HDL design modeling...
  verilog      Verilog     

Floating-point multiply verilog FPGA

Digital multiplier, as an integral part of modern computers, their design work and more and more people's attention. This paper, hardware description languages verilog HDL design a floating-point multiplier based on complement one multiplication and design functions and better flexibility. Th...
  verilog      Verilog     

I2C verilog

I2C verilog files. Define a simple interface of I2C. After testing to ensure the using....
  verilog      Verilog     

verilog serial port serial port receive module receiver module

verilog serial port serial port receive module receiver module, contains the BPS modules, level detection module and the control module...
  verilog      Verilog     

8,051 nuclear verilog source code

8,051 core RTL source code, with integrated testbench and scripts 8,051 core RTL source code, with integrated testbench and scripts 8,051 core RTL source code, with integrated testbench and scripts 8,051 core RTL source code, with integrated testbench and scripts 8,051 core R...
  verilog        ASM     

verilog float calculate

This code is used in verilog, to calculate 2 float numbers,which to be calculated nubmer are all32 bits,it can be used....
  verilog      Verilog     

PLL LMX2531 verilog Configurator

Source verilog programming, registers are used for configuring the PLL LMX2531, the output frequency is 1 GHz, has proven the value of the register, the clock output frequencies without problems, written with three-state machines, incidentally, one AD device configured, refer the reader to key refer...
  verilog      Verilog     

"Original" display __ __verilog_ _FPGA control _1602 debugging notes

FPGA control principle and LCD1602 debugging notes source code This information came from Baidu bases (http://wenku.Baidu.com/) You now see the document is used to hold rice Baidu base generated by the Download Manager This document's original address from Thank you for your support Hold rice...
  verilog      Verilog     

verilog code for the GPS baseband processing

GPS software receiver baseband processing verilog programs, by spread spectrum demodulation, intermediate frequency data synchronization process converts the raw navigation data...
  verilog      Verilog     

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