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8,051 nuclear verilog source code

8,051 core RTL source code, with integrated testbench and scripts 8,051 core RTL source code, with integrated testbench and scripts 8,051 core RTL source code, with integrated testbench and scripts 8,051 core RTL source code, with integrated testbench and scripts 8,051 core R...
  verilog        ASM     

PLL LMX2531 verilog Configurator

Source verilog programming, registers are used for configuring the PLL LMX2531, the output frequency is 1 GHz, has proven the value of the register, the clock output frequencies without problems, written with three-state machines, incidentally, one AD device configured, refer the reader to key refer...
  verilog      Verilog     

"Original" display __ __verilog_ _FPGA control _1602 debugging notes

FPGA control principle and LCD1602 debugging notes source code This information came from Baidu bases (http://wenku.Baidu.com/) You now see the document is used to hold rice Baidu base generated by the Download Manager This document's original address from Thank you for your support Hold rice...
  verilog      Verilog     

verilog code for the GPS baseband processing

GPS software receiver baseband processing verilog programs, by spread spectrum demodulation, intermediate frequency data synchronization process converts the raw navigation data...
  verilog      Verilog     

Digital Speed meter with rotation direction detection in verilog

This is a complete working module coded in verilog to detect the speed of rotations of a rotating wheel . Also it gives the direction of rotation . This can be directly implemented in a fpga board and within this module there's a special small module to generate the test signals for the metere . So...
  verilog      Verilog     

Code verilog for motion compensated prediction block of video

This is a project about VLSI design.Topic is design for motion compensated prediction block in compressed video.Project consisted Code RTL,Code Testbench.  Project use software of synopsys for example: Design Compiler (Synthesis),IC Compiler (Layout)......
  verilog      Verilog     

code verilog for cordic

This is a project about VLSI design.Topic is design for CORDIC (for COordinate Rotation DIgital Computer),also known as the digit-by-digit method and Volder's algorithm.Project consisted Code RTL,Code Testbench.  Project use software...
  verilog      Verilog     

radix 2 fft 32 bit using verilog

it provides source code for 32 point fft using verilog along with multiplier which describes butterfly unit using 32 bit multiplier along with carry look aheaada adder 32 bit using behavioural description.....
  verilog      Verilog     

verilog implementation of SMBUS bus

Two state machines and different modes of data transmission, as requested by the SMBus bus to regulate each transmission, from start to finish, to better achieve...
  verilog      Verilog     

FFT programs, based on verilog

FFT programs based on VHDL language, 256, rotation factor exists to write your own ROM inside, multipliers and data storage using IP core, if it needs to use, you need to add IP core, cannot be run...
  verilog      VHDL     

FPU Floating point unit verilog VHDL

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...
  verilog      Verilog     

SRAM_16bit_512K

SRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_ 512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512KSRAM_16bit_512...
  Embeded        C     

space exploration orbit design

space exploration,orbit design the aerogel cells were made to be slightly larger than the spaces machined out of ... aerogel also had to survive the transition from atmospheric pressure to the vacuum of space . ... RTG's are important to the continuing exploration of the outer solar system...
  Matlab        Matlab     

You can freely define the length of bits

bit of c++ templates can only be developed with constant size, redefine a bit here so that it can be defined with variables first, easier...
  Algorithm        C++     

CSA - carry select adder (16 bit by verilog)

this is CSA of 16 bit by verilog there are three kinds of them   one is made up of 2bits/group and the others are 4bits/group ,and 8bits/group...
  Algorithm      Verilog     

SPI (verilog)

SPI interface to start the program. Using the verilog language. Attach testbench. Verification by the appropriate changes can be applied to different...
  Driver Development      Verilog     

bits control

There's two only programs look no further, One can go towards any one change one simple bit 01, another 驗 witnesses been separated from its 01 is there really are changing, I like the DVD directly count on two-FA model. GE people their pretty easy to use, I ho...
  Embeded        C++     

128,192,256bit high standard algorithm

AES Is a new encryption standard, it is block cipher algorithm, the packet length 128 bit key length 128bit 、 192bit 、 256bit Three, respectively, AES-128 、 AES-192 、 AES-256 。 AES is composed of three parts, for encryption, key and decrypt extension . This article written in c language...
  Crypt_Decrypt algrithms        C     

verilog timing adder float

Very practical implementation of floating-point adder. Very practical implementation of floating-point adder. Very practical implementation of floating-point adder. Very practical implementation of floating-point adder. Very practical implementation of floating-point adder....
  Image Processing      Verilog     

verilog simulation of digital stopwatch for source

1 . 具有暂停/启动功能;2. With resume function;3. 6 digital tube display hundreds of seconds, seconds and minutes. Solution : On request, using a bottom-up design approach, opting for max+plus2 For editing and debugging. The whole is divided into two sections: one is co...
  Embeded      Verilog     

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