Search VHDL, 300 result(s) found

VHDL obtaining quadrature

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; Library UNISIM; use UNISIM.vcomponents.all; --------------------------------------------------------------------...

VHDL code for different adders

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- hi...

VHDL simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several parts through QuartusII 9 compiler testing is feasible. Code original containing syste...

VHDL code for latch_ff_comb for d_comb ckt in VHDL

library ieee; use ieee.std_logic_1164.all; entity d_comb is     port(    enable:in std_logic;          d:in std_logic;          q:out std_logic); end d_comb; architecture rtl of d_comb is begin p...

Learn VHDL displays a six-digit

During the eight-digit seven-segment digital display control display on 8-bit 学号 , To display the 的 学号 You can ride Sequence changes, device validation error-free and running well....

VHDL and verilog implementation of dds and fft

The core component of a DDS waveform generator is the accumulator. The accumulator is a running counter which stores the current phase value of the generated waveform. The rate at which the accumulator is updated and the accumulator increment value determine the frequency of the generated waveform....

VHDL sequential circuits

This circuit is a very simple VHDL sequential circuits through which circuit can clearly reactive VHDL timing principle as well as the most basic and simplest method of application,...

VHDL code for Adder / Subtractor

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY adder IS PORT(Cin        : IN STD_LOGIC; Carry        : IN STD_LOGIC;  X,Y        : IN STD_LOGIC_VE...

VHDL separator

VHDL PRograming its un aplicative tha it's performing at the memory ram  32 x 32 at rom 64 x 48...

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