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Simple Full Adder verilog code

This is a simple 1 bit full adder verilog code `timescale 1ns / 1ps module 1BitFullAdder ( input a, input b, input cin, output s, output cout ); assign s = a ^ b ^ cin; assign cout = (a & b) | (a & cin) | (b & cin); endmodule //Test Bench...
  Verilog      Verilog     

mux2x1 verilog code

module mux2x1(a,b,s,y); input a,b,s; output y; reg y;   always @(a or b or s) begin if(s==0) y=a; else y=b; end endmodule   module muxtop(x,s0,s1,a,b,c,d,x3,y3); input [7:0]x; in...
  verilog      Verilog     

Design module Bluetooth by verilog

The Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device. The main objective for this standard is to provide a royalty free standard for such wireless protocol. The objective of this project is to build an opensource free blueto...
  verilog      Verilog     

code verilog cordic core

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details...
  verilog      Verilog     

DDR2 controller, verilog source code

Using verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...
  verilog      Verilog     

verilog spwm

Second-class Prize in electronic design contests, implemented in the FPGA, two-way natural sampling SPWM...
  verilog      Verilog     

verilog for lsfr over bist

When desgin memories with larg portion, which include capacitance over bit-lines. The two bit-line are used perform a read and write operation, due to operation of discharging a capacitance in write operation. 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a...
  verilog      Verilog     

code verilog for motion compensated prediction block of video

This is a project about VLSI design.Topic is design for motion compensated prediction block in compressed video.Project consisted code RTL,code Testbench.  Project use software of synopsys for example: Design Compiler (Synthesis),IC Compiler (Layout)......
  verilog      Verilog     

code verilog for cordic

This is a project about VLSI design.Topic is design for CORDIC (for COordinate Rotation DIgital Computer),also known as the digit-by-digit method and Volder's algorithm.Project consisted code RTL,code Testbench.  Project use software...
  verilog      Verilog     

"Original" display __ __verilog_ _FPGA control _1602 debugging notes

FPGA control principle and LCD1602 debugging notes source code This information came from Baidu bases (http://wenku.Baidu.com/) You now see the document is used to hold rice Baidu base generated by the Download Manager This document's original address from Thank you for your support Hold rice...
  verilog      Verilog     

I2C verilog

I2C verilog files. Define a simple interface of I2C. After testing to ensure the using....
  verilog      Verilog     

Traffic light verilog

Finite state machine for a traffic light control, the whole project is added for working in ISE design suite from xilinx, and configured to be used in spartan 3, on a nexys 2 from digilent, has every archive and the project file, works for a two way traffic light, with sensors of traffic and pedestr...
  verilog      Verilog     

verilog UART model

the universal asynchronous receiver and transmitter is used in most microcontrollers and microprocessor the program describes the basic working of the uart model...
  verilog      Verilog     

DDR2 chip control module verilog

DDR2 memory module, we can learn from, including DDR2 internal clocks to refresh himself took a long time. Members may have their own internal clock frequency-chip depends on the situation. I am also a novice, may defect in many places in the code, we all learn together, thank you....
  verilog      Verilog     

verilog code for scrambler

In telecommunications, a scrambler is a device that transposes or inverts signals or otherwise encodes a message at the transmitter to make the message unintelligible at a receiver not equipped with an appropriately set descrambling device. Whereas encryption usual...
  verilog      Verilog     

flash_controller_verilog_code

附件为三星K9系列flash控制器的verilog代码,已经编译ok且在FPGA开发板上验证通过了,验证环境为quartusii和modelsim联合平台上。关于K9系列flash的datasheet,网友们可以自己到网站上去找。此项目的flash大小为1024*32。...
  verilog      Verilog     

FPU Floating point unit verilog VHDL

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...
  verilog      Verilog     

FIFO verilog code

this project gives a FIFO.Since the I2C bus can connects devices that operating on different data rates, First-In First-Out (FIFO) memory is need to suit the use of the I2C. with FIFO memory, a fast device can communicate with a very slow device through the FIFO buffer. In other hand, if fast an...
  verilog      Verilog     

PLL LMX2531 verilog Configurator

Source verilog programming, registers are used for configuring the PLL LMX2531, the output frequency is 1 GHz, has proven the value of the register, the clock output frequencies without problems, written with three-state machines, incidentally, one AD device configured, refer the reader to key refer...
  verilog      Verilog     

AMBA_AHB(amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde )

AMBA_AHB(amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde )...
  verilog      VHDL     

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