Search verilog, 300 result(s) found

SPI flash model written by verilog

M25Pxx ST company SPI flash memory verilog simulation model, the model correctly describes the behavior of SPI flash memory, including reading, writing and erase operations, can be used to hang outside of the SOC with SPI interface, verify that the SPI interface....

verilog LED spartan 6

This code is the verilog code, and spartan 6 model specification code. Welcome to download and try. Thank you for your support....

verilog for lsfr over bist

When desgin memories with larg portion, which include capacitance over bit-lines. The two bit-line are used perform a read and write operation, due to operation of discharging a capacitance in write operation. 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a...

verilog for booth multiplier

We are going to propose a new SRAM bitcell for the purpose of less power consumption, read stability,less area than the existing Schmitt trigger based SRAM and other existing designs through a new design which is combined of virtual grounding with Read error reduction logic.  ...

verilog spwm

Second-class Prize in electronic design contests, implemented in the FPGA, two-way natural sampling SPWM...

code verilog cordic core

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details...

verilog float calculate

This code is used in verilog, to calculate 2 float numbers,which to be calculated nubmer are all32 bits,it can be used....

verilog Code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...

verilog Arbiter

A four level, round-robin arbiter. This was orginally coded by WD Peterson in VHDL...

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