Search verilog, 300 result(s) found

SPI verilog source code

The Serial Peripheral Interface or SPI bus is a synchronous serial data link, a de facto standard, named by Motorola, that operates in full duplex mode. It is used for short distance, single  master communication, for example in embedded systems, sensors, and SD cards. Devices comm...

ALU verilog

The structure of an unsigned parallel multiplier is based on the observation that partial products in the multiplication process can be computed in parallel. Multiplication of signed operands, which generate a double-length product in the 2's-complement number system. The general strategy is...

verilog code for SDRAM

SDRAM driver, written in the verilog language, verilog reference those things is coming from, and is divided into three modules, initialize the module, the function module and the control module, the module which has a total of three modules together. 4bank row width column widths are 12-8-bit SDRAM...

AXI slave verilog implementation of agreements

AXI (Advanced eXtensible Interface) is a bus protocol, which was proposed by the ARM company AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol for the most part, is a high-performance, high-bandwidth, low-latency-oriented films Internal bus 。 It addresses/separation of control and data...

DDR2 chip control module verilog

DDR2 memory module, we can learn from, including DDR2 internal clocks to refresh himself took a long time. Members may have their own internal clock frequency-chip depends on the situation. I am also a novice, may defect in many places in the code, we all learn together, thank you....

fpga emif verilog

Interface Module, through the coding can achieve high addresses four separate functional modules configured in one FPGA, each functional module has a Output ports with FIFO and 13 independent DSP can read and write registers, register functions can be customized. The module also contains two gl...

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