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Verification of AND gate in system verilog
no vote
Description: To prepare aclass based layered test bench environment in SystemVerilog (SV) to verify a simple AND gate Responsibility: All the parts of testbench(Transaction, Generator/ Sequencer, BFM/Driver, Interface, Monitor, Checker/ Scoreboard,Agent and Environment) is developed in SystemVerilog. 
navathej
2016-08-23
0
1
Ethernet for FPGA-PC communication
no vote
Description: This projectwas to design an interface that enabled the FPGA board to communicate withother devices via the on-board Ethernet connection. Responsibility: Design of 10Base T Ethernet MAC has been done in verilog and implemented the same onSpartan 3E FPGA Board.  
navathej
2016-08-23
0
1
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