High efficiency and low power FFT algorithm based on FPGA and its implementation
no vote
&Improved the most famous Altera company's intellectual property (IP), & nbsp; & nbsp; & nbsp; source code using Altera HDL (. TDF) implementation, very complete, all Altera chips can use, radix-2 dif FFT algorithm, has been quartus development software and simulation software Modelsim joint test, simulation. The simulation results are very accurate, and the number of points can be changed in real time. The experimental results show that the operation speed of the 256 point complex base 2 FFT processor is 21.36us at 100MHz master clock frequency