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Aes_pipeline
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Application background The pipelined architecture of the AES algorithm is proposed in order to increase
the throughput of the algorithm.The inputs to the overall processor are as follows:
clk i: System Clock, Data I/O at rising edge
rst i: Asynchronous Reset, active high, initializes all inputs to all stages and the nal output to zero.
plaintext i: 168 bits plaintext input
keyblock i: 168 bits keyblock input
The output is
ciphertext o: 168 bits ciphertext output Key Technology The trunk/rtl/vhdl directory contains the whole source code.
The sample testbench is in trunk/bench/vhdl.
For compiling and running the testbench, the script sim isim.sh in trunk/sim/rtl sim/run directory
can be used for Xilinx ISim simulator and sim ghdl.sh for GHDL. The testbench takes in plaintext and
key data from vectors.dat in trunk/sim/rtl sim/src directory. The expected
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