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FPGA USB driver
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Application background Is the very first officially available release of the core This- is still under active development It- do not modify the sources Please!- that are not implemented yet or, are known not to work yet: Things - line/link control interface is not implemented yet. This includes: UTMI - of attach/detach Detection - negotiation Speed (Speed Full/High) - reset USB - suspend USB - is no logic in the core to help suspending There it. I'm not sure yet what to do in this area. quite (welcomed Suggestions!) - is no easy way to configure the core There (of endpoints number, size buffer) - has been absolutely no testing done on the core There Key Technology File describes the current status of the checked in HDL code. ThisSubmit all bugs/comments/suggestions regarding the USB core Please
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