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Nand_flash.vhd
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Application background Flash memory controller for SPI Protocol Key Technology -- nand_flash.vhd
-- Jacques Kleynhans 17/01/10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity NAND_FLASH is -- entity declaration
port (
clk : in std_logic; -- Input clock of the system is 40 MHz
mem_clk : inout std_logic; -- Clock generated by the pll1 to be 66.667MHz
rst_low : in std_logic; -- Reset of system is normally low
nand_cad : inout std_logic_vector(15 downto 0); -- CAD: command,address and data before ff
nand_rdy : in std_logic; -- Signal from the memory device, only accesible when high
nand_opr : in std_logic_vector(2 downto 0); -- Select between rd/wr/erase/rd_id/rd_st
nand_ce : out std_logic; --
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