Upload Code
loading-left
loading loading loading
loading-right

Loading

Profile
No self-introduction
codes (9)
Improve the throughput of Karatsuba AES-GCM FPGA o
no vote
Application background In this paper, we presented the throughput improvement of AES-GCM with pipelined Karatsuab-Ofman based finite field multipliers.With our proposed 4-stage sub-quadratic finite field multipliers, the GHASH function is not the bottleneck any more in GCM hardware systems, no matter which one of the three AES implementations is selected Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers 203 (BlockRAM based SubBytes, composite field SubBytes or LUT-based SubBytes). The presented AES-GCM cores reach the throughput of 31Gbps and 39Gbps on Virtex4 and Virtex5, respectively. The experimental results show that a single modern FPGA chip can provide the throughput of more than 30Gbps for the authenticated AES-GCM, which exhibits the advantage of field programmable devices in high performance computing systems. Key Technology Two main components
anu mohan
2016-08-23
0
1
An effective high throughput FPGA AES multi Gigabi
no vote
Application background In this paper, we have presented an efficient nonpipelined implementation of AES-128 to achieve high throughput so that it can be used in gigabit protocols. We have implemented our design of AES-128 encryption and decryption on a Xilinx Virtex-7 FPGA and achieved throughput of 5.30/ 4.86 Gbps in ECB mode and 5.23/4.84 Gbps in CBC mode. Key Technology Due to the requirement of high throughput architecture for encrypted channels, an efficient implementation of hardware is needed. This can be achieved by using smart utilization of high end reconfigurable platforms. To achieve convincingly high throughput, an efficient non-pipelined style implementation of Advanced Encryption Standard (AES) with key size of 128-bit, for multigigabit protocols on Field Programmable Gate Array (FPGA) is presented.
anu mohan
2016-08-23
0
1
Efficient implementation of advanced encryption st
no vote
Application background In this paper, a high performance and highly optimized hardware realization of Rijndael AES Algorithm has been designed and implemented on Xilinx Virtex-5 XC5VLX50 FPGA device. The design has been coded using modular approach by using VHDL Language. The design operates correctly as shown in the simulation result. The performance of the presented design is evaluated based on throughput and area. Our design utilizes a speed of 339.087 MHz, which translates to throughput of 4.34 Gbps using an area of 399 slices of a Virtex-5 FPGA. Key Technology This paper presents an efficient hardware realization of Rijndael Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing si
anu mohan
2016-08-23
0
1
A new FPGA implementation of S by reducing the res
no vote
Application background In this paper, we have presented a novel FPGA implementation of AES utilizing high performance S-Box which uses reduced residue of prime numbers. The proposed design was implemented on Xilinx Virtex-5 XC5VLX50 FPGA device. The objective is to use a novel S-Box based on LUT whose entries are set of residue of prime number. The S-Box with reduced residue of prime number adds more confusion to the entire process of AES algorithm and makes it more complex and provides further resistance against attacks. Our implementation achieves a throughput of 3.09 Gbps and uses a total of 1745 slices of a Virtex-5 FPGA. Key Technology The design of AES using reduced residue of prime number based S-Box is done using VHDL and implemented in a Xilinx Virtex-5 XC5VLX50 (package: ffg676, speed grade: -3) FPGA using the ISE 9.2i design tool. Ta
anu mohan
2016-08-23
0
1
FPGA core AES-GCM core 100G Ethernet Application
no vote
Application background in this paper, we propose an efficient design method to implement GCM combined with authentication encryption AES in reconfigurable hardware devices. With four AES cores and four binaryfields replicated, we can demonstrate how to break the 100gbps speed bound in FPGA. In order to reduce the critical path in ghash operation, a four stage pipeline has been inserted in GF (2128) multiplication. This final GCM architecture relies on a 4 × 4 architecture implemented in Xilinx Virtex-5 devices at 119gbps. Key technologies the upcoming IEEE Ethernet standard will focus on providing data transmission bandwidth of 100Gbit / US currently, the fastest encryption originally approved by the US National Institute of standards and technology, combining data encryption and identity authentication, is Galois / counter mode (GCM) operation. If it is feasible, the ASIC technology of increasing the speed from GCM to 100Gbit / s has shown that there are some important structural problems in the implementation of secure 100g Ethernet network system in GCM FPGA. In this paper, we report an efficient FPGA architecture that combines AES block cipher with this mode. With four pipelined parallel aes-gcm core, we can achieve the speed required by the new Ethernet standard. In addition, the authentication process of time critical binary field multiplication depends on four pipeline 2 Karatsuba human multipliers.
anu mohan
2016-08-23
0
1
A chain Merkle signature encryption processor arch
no vote
Application background One-time signature schemes rely on hash functions and are, therefore, assumed to be resistant to attacks by quantum computers. These approaches inherently raise a key management problem, as the key pair can be used only for one message. That means, for one-time signature schemes to work, the sender must deliver the verification key together with the message and the signature. Upon reception, the receiver has to verify the authenticity of the verification key before verifying the signature itself. Hash-tree based solutions tackle this problem by basing the authenticity of a large number of verification keys on the authenticity of a root key. This approach, however, causes computation, communication, and storage overhead. Due to hardware acceleration, this paper proposes, for the first time, a processor architecture which boosts the performance of a one-time signature scheme without degradi
anu mohan
2016-08-23
1
1
A 66.1 Gbps single pipe AES algorithm in FPGA
no vote
Application background Targeting real-time encryption/decryption of high speed data communication, this paper proposes an FPGA-based high throughput AES design. The critical functions involved in AES are broken into elementary logic operations to gain the deep insight into the performance bottleneck. With respect to FPGA structures, a datapath with two balanced pipeline stages is determined for each of the encryption/decryption rounds. Meanwhile, a new key expansion scheme with additional nonlinear operations is proposed to increase the security of the AES implementation and is well matched to the two-stage pipelining datapath. The design is evaluated on various FPGA devices and is compared with several existing AES implementations. Results show that in terms of both throughput and throughput per slice the proposed AES design with single pipeline can overcome most existing
anu mohan
2015-10-29
0
1
VHDL implementation of AES-128
no vote
Application background As in this whole work we are trying to reduce the delay by applying different techniques so need to work to minimize more delay as well as to implement the algorithm in Different applications as in Bluetooth, cloud computing etc. Key Technology Security has become an increasingly important feature with the growth of electronic communication. The Symmetric in which the same key value is used in both the encryption and decryption calculations are becoming more popular. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. This standard is based on the Rijndael algorithm. In this project our main concern is to implement all modules of this algorithm on hardware.This methodology uses VHDL implementation of all the modules in terms of Delay<
anu mohan
2015-10-29
0
1
Advanced Encryption Standard VHDL implementation
no vote
Application background security is no longer an afterthought development process of anyone's software design. AES is an important step forward, and using and understanding it will greatly improve the reliability and security of your software system. Because of the ability of FPGA to update features after shipping, part of the reconfiguration part of the design and low non recurring engineering costs can be used for the following applications. Key technology the new advanced encryption standard (AES) has recently been selected by the US government to protect sensitive social information. Because of its simplicity and elegant algebraic structure, the choice of AES algorithm is motivated by the study of a new method to analyze block ciphers. Advanced encryption standard can be in hardware software or built-in. However, field programmable gate array (FPGA) provides a faster, more customizable solution. Field programmable gate array (FPGA) is the perfect link or server for high speed communication system. This paper presents an efficient FPGA implementation of AES using VHDL. The design and implementation of AES encryptor is based on FPGA. AES decryptor is designed and integrated to produce a full-featured AES en / decryptor. VHDL is a hardware description language for ultra high speed integrated circuits. Xilinx software is used to simulate the comprehensive optimization of VHDL code. All encryption and conversion decryption use iterative design method in order to minimize hardware consumption.
anu mohan
2015-10-29
0
1
No more~