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Double precision floating point core Verilog
3.5
Application background IEEE-754 compliant double-precision floating point unit. 4 operations (addition, subtraction, multiplication, division) are supported, as are the 4 rounding modes (nearest, 0, +inf, -inf). This unit also supports denormalized numbers, which is rare because most floating point units treat denormalized numbers as zero. The unit can run at clock frequencies up to 185 MHz for a Virtex5 target device. Key Technology Features - The unit is designed to be synchronous to one global clock. All registers are updated on the rising edge of the clock.  - All registers
ducvv
2016-08-23
0
1
Low cost FPU
no vote
Application background The design aims to implement the minimum requirements of the IEEE-754 1985 standard for floating-point arithmetic, using simple algorithms with similar functional requirements. An important goal for the project is to provide a design that may offer the convenience of floatingpoint computations to the microcontroller domain, without a huge impact on hardware consumption or the slow execution speed of a software implementation. Implementation and specification is prioritized, but verification through simulation should be performed, in order to demonstrate the correctness of the final implementation. Key Technology The architecture can b e summarized as two distinct scalar pipelines, sharing a common control unit. In addition to this, an external multiplier is connected to the signicand pi eline. Certain o erations require some tr
ducvv
2016-08-23
1
1
Website checking robot
no vote
Application background Android security: the app will check and m onitoring the malicious URL and give warning to users . App using Safe Browser API of Google to check URL.  Safe Browsing is a Google service that enables applications to check URLs against Google's constantly updated lists of suspected phishing, malware, and unwanted software pages. Apps also using Web of Trust API to check URL and website <
ducvv
2016-08-23
0
1
Full line FPU for CPU OR1200
5.0
Application background Floating point unit has wide dynamic range of representable data and easy programming model, providing better precision than fixed point number system. In fact, various applications requires of using floating point unit, and the performance of floating point operations (FLOPS) is one of the major performance measure for a microprocessor. Current FPU on OR1200 CPU is implemented as serial components, therefore for each floating point operation, the pipeline inevitably stalls and wait for the floating point operation to be finished. According to the OR1200 specifications, the stall could take up to 38 clock cycles for floating point division operations. This result in very poor floating point operation performance and may significantly limit the potential application domain for OR1200 CPU. By implementing a pipelined FPU and integrate with the curr
ducvv
2016-08-23
1
1
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