input a,b,s; reg y; always @(a or b or s) if(s==0) else end input [7:0]x; output [7:0]a,b,c,d,x3,y3; wire [7:0]y0,y1,y2,y4; assign a=(x/8);
muralioxece
2016-08-23
00
1
LOGIC GATES USING GATE LEVEL OF MODELING
no vote
//INVERTER //input //output y;
muralioxece
2016-08-23
00
1
verilog and vhdl files
no vote
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tff1 is
port(
clk: in std_logic;
rst: in std_logic;
q1: out std_logic);
end tff1;