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The Verilog code instruction Cache
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16 bit CPU of Icache Verilog achieved code, each line 4 a Word, and through byte addressing, mapping way for directly mapping, using check table method..........................................................................................................................................
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Dcache design
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A DCache is designed, which connects two groups and uses LRU replacement algorithm............................................................................................. 。。。。。。。。。。。。。。。
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Icache design
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Icache a 16 bit DSP chip design, the design only for the corresponding scheme, the rate of Icache error control, through the simulation has to meet the basic requirements...............
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