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Sdram controller
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sdram controller codes for the in verilog .
in the first.rar---
matlab code is in first.rar
Find the zero skew clock rectilinear
tree for the sink distribution given in the MATLAB file- clockTreeAssignment.m.
Find delay(clock latency) from the root source
to the sinks. Use elmore delay-model(i.e
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VLSI DSP exercises
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The architectures present for adders and multipliers are in the verilog and are simulated in the cadence 45nm---report sheet with code (verilog)----reference vlsidsp by parhi
this is done by own
charantej--9524435535
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Residue number system
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A reverse convertor moduli set {2n+1,2n,2n-1} is proposed in this paper. Chinese Remainder Theorem is simplified
to get a reverse converter that uses mod-{2n-1} operations. Here the burden of explicit usage of the moduli is discarded .These reverse convertors are used to find the multiplicative inverse of the RNS value. In order to restrict the range we makes use of radix-8 booth modified rns multiplier in the proposed converter and the best equivalent state of the art converters on cyclone2 FPGA. when compare to other convertors this architecture saves power ,area,delay and cost reduced
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triple shift of negative numbers
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they r bit adders macha oekeokoekwkwadfgvmaeslf;ak qedkdfsmlaslkmdf,m
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