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Design of basketball 24 second controllable timer
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Using VHDL language to design basketball 24 second controllable timer function description: 1. It has 24 second timing and display function; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; 2. Set external keys to complete reset, pause and resume control; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; 3.24 second countdown, time interval is 1s; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; & nbsp; 4. When the time is up, the alarm signal will be sent out and released after 3S.
addygq89@sina.com
2018-05-21
0
1
Verilog implementation of matched filter
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Implementation of matched filter based on Verilog using quatusii tool
addygq89@sina.com
2018-05-11
0
1
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