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FPGA implementation of divider
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A divider is designed, which can run on the basys2 development board. The divisor is 16 bits, and the divisor is 8 bits. Both the divisor and the divisor are input with the key. The result is displayed with the nixie tube. An enable switch is set, and the operation is carried out when the switch is turned up. As the number of resources such as nixie tube and key is small, the following scheme can be considered. Two switches are used to determine the state, such as SW1 and SW0. When sw1-sw0 is 00, it is used to input the divisor, 4-bit hexadecimal number is input through four keys, and the input number is displayed through the nixie tube; when 01, it is used to input the divisor, 2-bit hexadecimal number is input through two keys, and the input number is displayed through the nixie tube; when 10, it is displayed as quotient; when 11, it is displayed as remainder.
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