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The code of controlling ST16C2550 based on Verilog HDL
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St6c2550b provides synchronous processing of serial asynchronous receiving data, parallel serial and serial parallel conversion of data between transmitter and receiver. These functions are necessary for the digital data system to convert serial data stream into parallel data stream. The synchronization of serial data stream is realized by adding a start bit and a stop bit to the transmitted data to form a data character (character transfer protocol in the specified direction). The integrity of data can be guaranteed by adding a parity bit after the data character. The receiver checks for errors in any transmit bit by the parity bit. Electronic circuit can realize these functions, but it is very complex, especially to integrate them into a silicon chip. Sc16c2550b is the representative of such an integrated chip with enhanced characteristics, which is made of advanced CMOS technology. The controller is designed by Verilog HDL to control the ST16C2550 chip and realize the data transmission between the serial port and DSP. According to the timing and logic requirements of the technical manual, the controller is designed. To control the ST16C2550 chip, the controller needs to have chip selection port, read-write port, address port, data transceiver port and reset port to connect with the chip. ST16C2550 is configured and transmitted by address port and data transceiver port. After the controller is programmed, it uses Modelsim and signaltap to simulate the hardware and software. The simulation completes the hardware debugging and realizes the set function.
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